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TowerJazz — Interview With SVP Marco Racanelli: What’s Driving Strong SOI-Based Design Wins?

Dr. Marco Racanelli, TowerJazz Senior Vice President & General Manager, RF & High Performance Analog Business Group and Aerospace & Defense Group

Dr. Marco Racanelli, TowerJazz Senior Vice President & General Manager, RF & High Performance Analog Business Group and Aerospace & Defense Group

 

 

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ASN recently spoke with TowerJazz SVP Marco Racanelli about when the specialty foundry leverages SOI – and why.

Advanced Substrate News (ASN): Can you tell us briefly about TowerJazz’s overall vision and position in the market? 

Marco Racanelli (MR):  TowerJazz is the foundry leader for the manufacture of specialty semiconductor devices.  By “specialty” semiconductor devices, we mean those that require technology with some degree of specialization beyond commodity CMOS, for example in applications such as analog, RF, power, CMOS Image Sensor, and MEMS.  We invest in specialty process technology and manufacturing capacity around the world to fuel our growth (today we have manufacturing facilities in the US, Israel and Japan).

The TowerJazz fab in Newport Beach, CA.

The TowerJazz fab in Newport Beach, CA.

ASN: What kinds of chips does TowerJazz propose customers put on SOI? Why? 

MR: SOI on high resistivity substrates provides excellent RF isolation for customers working on front-end modules (FEMs) for wireless communication products.  Specifically for RF switches, thin device silicon layers result in low junction capacitance which is favorable for achieving high isolation.  We have had some customers leverage our SiGe BiCMOS technologies on SOI to integrate improved RF switching capabilities and achieve better isolation among circuit blocks.  Finally, some TowerJazz customers use thick film SOI for MEMS.  The silicon layer in SOI is used to fabricate beams for electro-mechanical structures and devices, e.g. MEMS resonators.

ASN: What are the growth drivers (end-markets, trends) for your SOI-based services? 

MR: Each generation of smart phones has required increasing numbers of RF ports to support multiple standards and functions e.g. 3G, 4G, 802.11, diversity antenna.  The need for longer handset battery life is driving implementation of RF-SOI based antenna tuner products to improve antenna efficiency.

 

Click to enlarge. (Courtesy: Techinsights’ Teardown.com and IEEE S3S Conference)

Click image to enlarge. (Courtesy: Techinsights’ Teardown.com and IEEE S3S Conference)

ASN: What are the advantages in moving to SOI-based technologies? 

MR: In some markets such as FEMs, the performance advantages of SOI are required to enable these RF products in CMOS; bulk technologies simply can’t provide the required isolation and low capacitance to meet the most demanding 4G/LTE specifications.  Thicker film SOI can support SiGe bipolar devices with significantly lower collector-to-substrate capacitance than their bulk counterparts.  In high voltage products, SOI dielectric isolation can simplify the design process, reduce latch-up risk, and allow a much more compact design than junction-isolated technologies.

Inside the TowerJazz Newport Beach Facility (Fab 3)

Inside the TowerJazz Newport Beach Facility (Fab 3)

ASN: Are there particular regions where you see especially high growth for SOI-based offerings? 

MR: We see broad adoption of SOI in all major phone platforms.  Our strongest growth and largest market for SOI is in the US although we see some Asia customers as well. The end customers are more evenly distributed between the US and Asia primarily.

ASN: Last year, you announced your RF-SOI had the industry’s best figure of merit for antenna switch and antenna tuning applications. What are you seeing there in terms of design wins? 

MR: We are seeing very strong design wins and production ramp of SOI in our factories.

 

American Semiconductor's  FleX-MCU™ product family leverages an SOI starting wafer.  (Courtesy: American Semiconductor)

American Semiconductor’s FleX-MCU™ product family leverages an SOI starting wafer.
(Courtesy: American Semiconductor)

ASN: American Semi partnered with TowerJazz on flexible ICs, which leverage SOI.  What sort of applications is that technology going into?  

MR: The potential for flexible ICs is very broad. For Aerospace and Defense, key areas of interest are ‘wearable’ circuits, introducing ICs and systems into soldiers’ field clothes and gear, creating a radar system that conforms to the entire body of an aircraft, sea vehicle, or any UAV or drone.  The ideas can be countless – the path is to reduce or eliminate the rigid form and fit of mobile electronics and integrate these electronics into a lighter weight, smaller and more flexible material.

ASN: Cavendish Kinetics announced that they’d be collaborating with you on RF-MEMS for mobile, which could be on SOI.  Is that available, and if so, can you tell us about it?

MR: We continue to work with Cavendish and have announced impressive reliability results with their devices; these are available through Cavendish directly.

ASN: Can you tell us more about the forthcoming 0.18 TS18SOI integrated power platform? 

MR: This platform is targeting a number of applications, the dominant one being in automotive and will include high-voltage devices, 0.18um CMOS for integration of digital and power management functions along with non-volatile-memory.  SOI in this case helps isolate the devices from the substrate allowing flexibility in applying voltages without turning on junctions that can lead to leakage or latch-up and in some cases helps reduce die-size by improving isolation allowing devices to be closer together.

ASN: Looking down the road, where/how do SOI-based technologies fit into your outlook for the future?  

MR: SOI particularly for RF is a significant focus for TowerJazz and we continue to invest in new technology and propagating the technology we have to multiple factories to increase capacity available to our customers.  While RF dominates our SOI consumption, we also see a good future for SOI in power management and MEMS and other sensor applications.

 

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TowerJazz will be presenting its SOI and other processes at its upcoming Technical Global Symposiums (TGS) taking place in Europe (18 September 2014), the US (19 November 14) and Japan (10 December 2014). To find out more and register for TGS, please visit: http://www.towerjazz.com/tgs/

 

 

 

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Dr. Marco Racanelli has served as TowerJazz Senior Vice President & General Manager, RF & High Performance Analog Business Group and Aerospace & Defense Group since September 2008. Previously, he served as Vice President of Technology & Engineering, Aerospace & Defense General Manager for Jazz Semiconductor.

 Prior to Jazz, Dr. Racanelli held several positions at Conexant Systems and Rockwell Semiconductor since 1996 in the area of technology development where he helped establish industry leadership in SiGe and BiCMOS and MEMS technology, and built a strong design support organization. Prior to Rockwell, Dr. Racanelli worked at Motorola, Inc., where he contributed to bipolar, SiGe and SOI development for its Semiconductor Products Sector.

 Dr. Racanelli received a Ph.D. and a M.S. in Electrical and Computer Engineering from Carnegie Mellon University, and a B.Sc. in Electrical Engineering from Lehigh University. He holds over 35 U.S. patents.

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FD-SOI: The Best Enabler for Mobile Growth and Innovation

The following in-depth analysis, an IBS study entitled How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales, concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics. In fact, FD-SOI has the ability to support three technology nodes, which can mean a useful lifetime through 2020 and beyond for digital designs and through 2030 for mixed-signal designs. Here are some of the highlights from the study.

First, let’s consider the markets we’re addressing.

The unit volume of smartphones and tablet computers is projected to reach nearly 3B units in 2020 worldwide. These mobile platforms need to have access to low-cost and low-power semiconductor products, including application processors and modems. Performance must also be enhanced, but this needs to be done within the cost and power consumption constraints.

Mobile platforms need essentially the same performance as notebook computers, but have to rely on much smaller battery capacity. They also need to support high-performance graphics and ever-greater data rates, including the support of 1Gbps when the 5G protocol is tested in 2018. Better cameras demands high-performance image signal processing. 3-D imaging, now under development, will require multiple image sensors. All of this needs to be accommodated with lower power consumption and lower cost.

It is significant that a high percentage of smartphones and tablet computers will be manufactured byChinese companies. Semiconductor technologies that increase battery lifetime without incurring additional costs or potentially providing lower cost can be very attractive to smartphone vendors.

The market requirements are clear, and our detailed analysis of various technology options, including bulk CMOS at 28nm and 20nm and FinFET at 16/14nm, shows FD-SOI is the best option for supporting the requirements of high-volume mobile platforms.

 

FinFET Realities

FinFETs have the potential to be in high volume in the future: the key issue is timing. Our analysis indicates that FinFETs have high design costs, along with high product costs. It is not realistic to expect FinFETs to be effective for the low-cost and low-power modems, application processors, and other processor engines for mobile platforms in 2016 and 2017.

FinFETs need to go through two phases in the 2015 to 2016 time frame to reach the point where they are suitable for low power and low cost applications.

In the first phase, they will be used in high-performance products such as processors for servers, FPGAs, graphics accelerators, and other similar product categories. This approach was used in the past for new-generation process technologies, where price premiums were obtained from the initial products. The time frame for the high-performance phase of 16/14nm FinFETs within the foundry environment can be 2015, 2016, and potentially 2017.

The high-performance phase can allow extensive characterization of the 16/14nm process and provide a good understanding of various categories of parasitic so that product yields can become high. There is also the need to establish design flows so that new products can be brought to the market within short design windows. The high priced product phase can position 16/14nm FinFETs to be potentially used in high volume, low cost products at a future time.

The second FinFET phase comprises the ramp-up to high volumes for high end processor engines for mobile platforms. High-end mobile platforms, including tablet computers and smartphones, can provide relatively high volumes for FinFET products if costs are competitive. Modems, application processors, and graphics functionality will be suited to the 16/14nm FinFETs from the foundries in the 2017 to 2018 time frame.

This type of methodical approach in solving the manufacturing challenges at 16/14nm can be applied to 10nm and 7nm FinFETs. There is the need to establish design flows that can yield high gate utilization as well as the ability to obtain high parametric yields. The time frame for the high-volume, low-cost phase of FinFETs can potentially be 2017 or 2018.

With the delays in ramping 16/14nm FinFETs into high volume until potentially 2017 or 2018, an alternate technology is needed to support the next phase of the mobile platform IC product supply, which can give low power consumption and low cost.

 

FD-SOI: Competitive Positioning

 To provide visibly into the options for technology selection, IBS has analyzed projected wafer costs and gate costs for bulk CMOS, FD-SOI, and FinFETs. Considerations include processing steps, masks, wafer costs, die shrink area, tool depreciation and parametric yield. The results are shown in the following figures.

 wafercosts (2)  gatecosts (2)

Processed wafer cost comparison for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)

Gate cost comparison  for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)

 

The low cost per gate of 28nm wafers in Q4/2016 and Q4/2017 allows this technology node to have a long lifetime. The performance of 28nm FD-SOI is 30% higher compared to 28nm bulk CMOS, with leakage also being 30% lower. There are, consequently, significant benefits in using 28nm FD-SOI compared to 28nm bulk CMOS for the high volume cost- and power-sensitive applications.

 Furthermore, the performance of 28nm FD SOI is 15% better than 20nm bulk CMOS, giving 28nm FD-SOI a potentially even longer lifetime.

 The gate cost of 20nm FD-SOI is 20%  lower than 20nm bulk CMOS, while offering 40% lower power. and 40% higher performance. The higher cost per gate of 20nm bulk CMOS compared to 20nm FD-SOI is due to the higher number of processing and masking steps. There are also parametric yield penalties at 20nm because of difficulties in controlling leakage. Fabless companies that choose 20nm bulk CMOS over 20nm FD-SOI (called 14nm by STMicroelectronics) risk to find themselves with a noncompetitive platform.

 14nm FD-SOI (called 10nm by STMicroelectronics) has an almost 30% lower cost per gate than 14nm FinFETs (including 16nm FinFETs) in Q4/2017, which is a major advantage in price-sensitive applications. Power consumption and performance are expected to be comparable between two technologies.

 

Why the hesitation in using FD-SOI?

While we clearly see that the benefits of FD-SOI, we also recognize that there is an expectation in the semiconductor industry that Intel sets the bar, so if Intel is doing FinFETs, everyone else should, too. The financial metrics of Intel are, however, different from those applicable to the fabless-foundry ecosystem. Intel is obtaining large revenues from its data center processors. And even though the company has promoted its 14nm and Tri-Gate processors for mobile platforms, Intel’s success in this arena has not been outstanding to date. Intel has, however, delayed the high-volume production of its 14nm Tri-Gate from Q4/2013 to H1/2015 because of low yields. The yield challenges that Intel is experiencing at 14nm should be a warning to fabless-foundry companies of the difficulties in ramping 16/14nm FinFETs within relatively short time frames.

Nonetheless, the manufacturing ecosystem is committed to making FinFET successful, so the resources that have been committed to FD-SOI have been limited. There is also reluctance to admit that the decision to adopt FinFET was premature and a thorough analysis of the cost penalties was not done. A similar perspective applies to 20nm bulk CMOS in following the industry pattern for not having a thorough review of the cost and performance impact.

 

FD-SOI for High-Volume Applications

The benefits of FD-SOI are clear, and as the yield and cost problems related to 20nm bulk CMOS and 16/14nm FinFETs become clearer, it is expected that there will be increased momentum to adopt FD-SOI at 28nm, 20nm (14nm by STMicroelectronics), and 14nm (10nm by STMicroelectronics).

To recap, FD-SOI provides the following benefits for high-volume mobile multimedia platforms:

  • At 28nm, FD-SOI has lower gate cost than bulk CMOS HKMG through Q4/2017.
  • 28nm FD-SOI performs 15% better than 20nm bulk CMOS HKMG.
  • At 20nm, FD-SOI has lower power consumption than bulk CMOS and lower cost per gate, (about 20% lower in Q4/2017). FD-SOI also has lower power consumption or higher performance compared to bulk CMOS.
  • Shrinking FD-SOI to 14nm yields about 30% lower gate cost in Q4/2017 than 16/14nm FinFET, with comparable performance and power consumption levels.

At 28nm, 20nm, and 14nm technologies, IBS concludes that FD-SOI is superior to competitive offerings for smartphones and tablet computers, and the advantages of FD-SOI extend through Q4/2017. As the supply base for FD-SOI strengthens, FD-SOI is expected to become a key part of the semiconductor supply chain ecosystem for high-volume applications such as smartphones and tablet computers.

The ecosystem in the semiconductor industry should focus on the technologies that optimize the benefits for customers.

Interview: Leti CEO Malier on the FD-SOI Breakthrough; Leti Days in Grenoble (24-26 June) & Semicon West

Some years back, European research giant CEA-Leti made a major commitment to support FD-SOI, partnering with STMicroelectronics, Soitec and IBM.  Now, with the big FD-SOI foundry announcement by Samsung and STMicroelectronics, Leti’s ready to bring its vast expertise to players throughout the value chain, right up through design integration.

To learn more about the range Leti covers, you may also want to check out the “Leti Day” conferences around the world, where they showcase their technology. The next one is in Grenoble (24-26 June, registration site here), followed by an invitation-only event during Semicon West (info here), as well as events in Paris and Tokyo.

ASN recently caught up again with Laurent Malier, CEO of CEA-Leti to get his take on the ST-Samsung news.  (A few months ago, we did an in-depth interview with Malier on the massive role Leti plays in the FD-SOI ecosystem — click here to read it if you missed it then).

LaurentMalierLeti

Laurent Malier, CEO of CEA-Leti

Here are some excerpts from our conversation.

Advanced Substrate News (ASN): What does the Samsung-ST announcement mean for Leti?

Laurent Malier (LM): It means the success of our strategy. For years, we’ve been heavily investing in FD-SOI technology, committing critical scientific and technological support at each phase of FD-SOI development. We were very confident that it was the best option for balancing performance, energy efficiency and cost.  In terms of technology and performance, that was very clearly demonstrated last year at CES and in Barcelona. In addition to performance you need to go into manufacturing, secure the ramp-up, secure the costs, and secure the full ecosystem. We worked very hard on all these things over the last year and a half. But the last brick was missing: securing a foundry for the second source and enlarging access to the technology. Now we have it: the ST-Samsung announcement gives us the opportunity to showcase our work and our methodology

 

ASN: In which areas did Leti contribute to FD-SOI development?

LM:  Leti really took a global approach in the development of FD-SOI. Of course, the SOI substrate is based on a Leti invention.  Device research was done by Leti teams with our ecosystem of partners at three different sites, first in Grenoble, and later at Crolles [ST] and Albany [IBM]. We were also active in the modeling (UTSOI models implemented in all EDA tools were developed by Leti) and design kit development, so that a complete design kit was available for designers. We had designers who worked for several years in order to prove the results at the circuit level. And we have several customers for whom we’re deploying the technology in their applications. So from raw material to architecture and application design, we have a global footprint.

Because FD-SOI is an enabling technology, we need to do more than support the “push” – we also need to support the “pull” in exploring applications that will benefit from this technology. This is something else we do. Leti is not only a silicon technology institute but also is focused on applications. Half of our activity looks at application opportunities – especially for telecom, IoT, healthcare, automotives and power management.

 

ASN: Do you see opportunities for FD-SOI in IoT?

LM: For me, the first wave of IoT will be in machine-to-machine [M2M] and process monitoring, so that’s synergistic with sensors. Because your objects are connected, you’ll greatly expand your ability to explore data.  You’ll need more efficient local data processing and more efficient data transmission – so these are places for FD-SOI circuits. For companies that are interested in any part of the value chain – design, sensor integration and so forth – these are areas where we are leaders and can provide expertise.  Look for more announcements coming up at Leti Days.

LetiDays2014

Soitec and Simgui (China) Partner on SOI Wafer Production for RF and Power Apps

Soitec and Simgui (Shanghai, China) are partnering on SOI wafer production for RF and power applications. The newly signed deal (read press release here) includes a licensing and technology transfer agreement. Simgui will establish a high-volume SOI manufacturing line using Soitec’s proprietary Smart Cut™ technology to directly supply the Chinese market. In addition, Simgui will manufacture Soitec’s 200 mm SOI wafers for the global market outside China, expanding Soitec’s supply to customers worldwide. Beyond this initial cooperation, the two companies plan to expand their collaborative efforts in the future to take advantage of their synergies.

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

IEEE S3S conference

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.

Today, we would like let you know that the advance program is available, and to attract your attention on the incredibly rich content proposed within and around this conference.

The conference revolves around an appropriate mix of high level contributed talks from leading industries and research groups, and invited talks from world-renowned experts.

The complete list of posters and presentations can be seen in the technical program.

This year some additional features have been added, including a joint session about RF CMOS as well as one about 3D integration.  Check the list of participants on those links, and you will see that major players in the field are joining us!

Our usual rump session will let us debate what the 7 nm node and beyond will look like, based on the vision presented by our high profile panelists.

(Photo Credit: Monterey County Convention and Visitors Bureau)

(Photo Credit: Monterey County Convention and Visitors Bureau)

There will be 2 short courses this year, and 2 fundamentals classes.  Those educational tracks are available to you even if you do not register for the full conference.

On Monday October 7th, you can attend the short course on “14nm Node Design and Methodology for Migration to a New Transistor Technology“, that covers specificities of 14nm design stemming from the migration of classical bulk to bulk to FinFET/FDSOI technologies..

Alternatively, on the same day you can attend the “3D IC Technology” short course, introducing the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects due to the Through Silicon Via (TSV).

On the afternoon of Wednesday October 9th, you can opt to follow the Sub Vt Fundamentals Class on “Robust subthreshold ultra-low-voltage design of digital and analog/RF circuits” or the SOI Fundamentals Class “Beyond SOI CMOS: Devices, Circuits, and Materials “.

You could also prefer to take the opportunity to visit the Monterey area.

Cannery Row at twilight

(Photo credit: Monterey County Convention and Visitors Bureau)

The conference has always encouraged friendly interactions between the participants, and because it covers the complete chain, from materials to circuits, you are sure to meet someone from a field of interest.  The usual social events, welcome reception, banquet and cookout dinner, will provide you with more openings for networking, contemplating new project opportunities or getting into technical discussions that could shed new light on your research.

To take full advantage of this outstanding event, register now!

Please visit our Hotel Registration Information page to benefit from our special discounted room rates at the conference venue, The Hyatt Regency Monterey Hotel and Spa.

The latest conference updates are available on the S3S website (http://S3Sconference.org).

PCMag’s Michael Miller called IBM’s 22nm SOI Power8 “the most fascinating” of the high-end processors

397604-ibm-power8PCMag’s Michael Miller called IBM’s 22nm SOI Power8 “the most fascinating” of the high-end processors. Reporting on this year’s Hot Chips conference, presented there. He noted that the chip “will have 12 cores, each capable of running up to eight threads, with 512KB of SRAM Level 2 cache per core (6MB total L2) and 96MB of shared embedded DRAM as a Level 3 cache.” He cites the eDRAM, which ASN readers first learned about in an ’06 article by Subi Iyer, the IBM father of eDRAM – when he explained, “The complexity adder is about half in SOI compared to bulk for deep trench based eDRAMs.”

Miller also says, “Compared with the previous generation Power 7+, which was manufactured on a 32nm SOI process, Power8 should have more than twice the memory bandwidth at 230GBps. IBM says each core should have 1.6 times the performance of Power7 on single-threaded applications and twice the SMT (symmetric multi-threaded) performance.”

ST’s FD-SOI Wins EETimes ACE Award… and Customers!

Two important FD-SOI wins for STMicroelectronics have just been announced:

  1. The EETimes ACE Award for Energy Technology;
  2. Customers.

ACE award logoThe Energy Technology Award was presented at a ceremony for the 2013 Annual Creativity in Electronics (ACE) Awards. It is given by EETimes and EDN, two of the most prominent trade-media sources in electronics. The ACE Awards honor the people and companies behind the technologies and products that are changing the world of electronics and shaping the way we work, live, and play.

Why the energy category?  ST attribututes it to FD-SOI’s ability to reduce energy consumption and carbon emissions in two important ways.  First, manufacturing FD-SOI is simpler and requires 15% fewer process steps than equivalent traditional silicon technologies and far less than complex alternatives to achieve similar performance, thereby using less energy per wafer produced. Moreover, products manufactured using FD-SOI technology show energy savings between 20 and 50%, making end-user devices run cooler and last longer.

FD SOI ACE Award

Accepting the EEtimes ACE Award for STMicroelectronics’ FD-SOI technology: Joel Hartmann, Executive Vice President of Front-End Manufacturing & Process R&D, Digital Sector; and Philippe Magarshack, Executive Vice President, Design Enablement & Services.

Commenting on the award, Executive Vice President of Front-End Manufacturing & Process R&D, Digital Sector Joel Hartmann said, “The Energy Technology Award confirms that FD-SOI is a game-changing technology that addresses the low-power and high-performance needs of the market. It also empowers chipmakers to deliver products meeting the dual benchmark of industry-beating “performance per watt” and “performance per watt per dollar.”

And of course, ST’s FD-SOI is ready for manufacturing now: it’s a faster, simpler and cooler upgrade to traditional semiconductor manufacturing at process nodes of 28nm and below.

Which is why we’re now starting to hear about customers!  Here’s what they had to say at their Q1 2013 Results – Earnings Call (the transcript was just posted on Seeking Alpha).

“In Digital Convergence, I’m pleased to say we earned important design wins in the FD-SOI advanced CMOS technology, the next-generation process technology that ST is pioneering,” said Carlo Bozotti, Chairman of the ST Managing Board, CEO and President in his opening remarks.

In a follow-up question from a BNP Paribas analyst, he added, “On the FD-SOI, we are working very aggressively on two fronts. The first front is communication infrastructure. We believe this is an area where the value of lower power dissipation for the same processing power / performance is important. Sometimes it is very important. And we have won the first project for this kind of application. However, there is another target area that is portable equipment, but not necessarily smartphone. There are other, I would say, great opportunities and some of these are really important opportunities that are outside the smartphones and outside the tablets, but they are very important opportunities. And, hopefully, we will have some more good news in the near future.”

Asked if it could be licensing revenues, he replied, “This is something that is possible.”

DARPA reports that a team of researchers at the University of Southern California and Columbia University has achieved output power levels of nearly 0.5W at 45 GHz with a 45nm SOI CMOS chip

Darpa RFPA SOI Columbia

(Image courtesy of DARPA and Columbia University)

DARPA reports that a team of researchers at the University of Southern California and Columbia University has achieved output power levels of nearly 0.5W at 45 GHz with a 45nm SOI CMOS chip. This world record result for CMOS-based power amplifiers doubles output power compared to the next best reported CMOS millimeter-wave power amplifier. The chip design used multiple stacked 45nm SOI CMOS devices for increased effective output voltage swing and efficient 8-way on-chip power-combining. Results will be reported at the 2013 Institute of Electrical and Electronics Engineers Radio Frequency Integrated Circuits Symposium. RF power amplifiers are used in communications and sensor systems for next-generation military microsystems in areas such as radar, guidance and high data rate communications to boost power levels for reliable transmission of signals over the distance required by the given application. These breakthroughs were achieved under the Efficient Linearized All-Silicon Transmitter ICs (ELASTx) program.

Wafer Leaders Extend Basis for Global SOI Supply

Soitec Shin-Etsu

It’s a bright green light from the world leaders in SOI wafer capacity. Soitec, the world leader in SOI wafer production, and long-time partner Shin-Etsu Handatai (SEH), the world’s biggest producer of silicon wafers, have extended their licensing agreement and expanded their technology cooperation.

SEH is a $12.7 billion company, supplying over 20% of the world’s bulk silicon wafers. SEH’s relationship with Soitec goes way back: they were one of the original corporate investors back in 1997, and the first to license Soitec’s Smart CutTM technology for manufacturing SOI wafers.

With its 300mm SOI wafer production fabs in France and Singapore, Soitec has an expandable installed industrial base of two million wafers per year.

As Horacio Mendez, Executive Direct of the SOI Consortium told ASN, “This is a very significant announcement. The substrate supply chain is fully engaged: we have multiple independent suppliers that can clearly meet the market demands for all key sectors, including mobile devices. As the advanced technology nodes ramp, the wafer production is in place; and very importantly, the capacity is expandable to provide maximum flexibility to customers.”

SEH has been manufacturing standard SOI wafers using Smart Cut technology for years. And last year, the company said it had completed development of its ultra-thin BOX (aka UTB — the wafers used for planar FD-SOI) substrates. Nobuo Katsuoka, director of the SOI program at SEH, recently told Semiconductor Manufacturing & Design, “SEH is delighted to deliver the products on request.”

Wafers for FD-SOI (a “planar” “2D” technology) have Angstrom-level uniformity in their ultra-thin layers – so it’s excellent news that the the industry’s two leaders are both supply sources.

SOI wafers for FinFETs (a “vertical” or “3D” technology, for which the top silicon and insulating BOX layer don’t have to be ultra-ultra-thin) have also long been available from Soitec, SEH and other sources.

With respect to this announcement, SEH’s Katsuoka said, “We are very excited about the business opportunities for SOI products, and we look forward to working with Soitec to extend the global supply chain for new products, such as FD-SOI and SOI for FinFETs, which are showing potential benefits in mobile and embedded applications. Our relationship with Soitec has been a very positive and fruitful one, and we are excited to extend that collaboration. The unique features of Smart Cut will enable our two companies to jointly improve global output for existing and new SOI products.”

As Steve Longoria, SVP of WW Business Development at Soitec, told ASN, “The wafer is the front end of the manufacturing process. This announcement is a proof point of new energy for robust, multi-source supply for impending high-volume demand.”

Soitec SOI wafers

Beyond logic

The newly announced Soitec-SEH agreement also extends the companies’ commitment to wafers for a broad-range of areas. For example, there are major market opportunities in SOI for RF devices, power, MEMS/sensors, photonics and more.

The agreement also extends to R&D for technologies of the next wave. We might think of Smart Cut as an SOI technology, but in fact it’s really a manufacturing technology that can be applied to a huge range of wafer materials. As a result of the extended agreement, SEH will continue to use Soitec’s industry-defining Smart Cut technology to manufacture SOI wafers, and now will be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), which will allow SEH to further expand its scope of applications.

So with an abundance of opportunities, a robust multi-source supply chain for the front end of the chip manufacturing process, top-quality wafers that enable savings and efficiencies – in short, better end-user value – it’s all systems go for high-volume demand.

Soitec Smart Cut

This illustration shows how Smart Cut, Soitec’s proprietary engineered wafer technology, works. The industry standard, this revolutionary wafer bonding and layer splitting processes makes it possible to transfer a thin layer of material from a donor substrate to another substrate, overcoming physical limitations and changing the face of the substrate industry. The Smart Cut technology was originally developed by the CEA-Leti. Soitec holds exclusive exploitation of CEA-Leti rights into the Smart Cut technology, including the right to sublicense to SEH. The technology was made viable for SOI high-volume commercial production by Soitec, and is now protected by more than 3,000 patents owned or controlled by Soitec.

NXP has named SOI wafer-leader Soitec as this year’s recipient of the “Best Supplier – Valued Partnership” for the company’s SOI solutions

NXP has named SOI wafer-leader Soitec as this year’s recipient of the “Best Supplier – Valued Partnership” for the company’s SOI solutions. NXP uses Soitec’s wafers in many of its most successful products for high-volume markets including power, automotive and lighting. The two companies have worked together since 1995.