Tag Archive silicon-on-insulator

Successful RF-SOI 2014 International Symposium Held in Shanghai

A very successful international workshop on RF-SOI was held in Shanghai earlier this fall.  Jointly organized by industry leaders, it brought together world-class players in RF to discuss the opportunities and challenges in rapid development of RF applications.Sponsors included the SOI Industry Consortium, the Chinese Academy of Sciences (CAS) / Shanghai Institute of Microsystem and Information Technology (SIMIT), Shanghai Industrial μTechnology Research Institute Co.,Ltd. (SITRI) and VeriSilicon.

The first talk, given by Dr. Xi Wang, Academician of CAS and Director General of SIMIT, covered China’s huge market prospects for RF applications. RF-SOI, he noted, is an area in which Shanghai Simgui Technology Co.,Ltd. ,  a spin-off company from SIMIT,  and French SOI wafer manufacturer Soitec are working closely to explore the market opportunities now. He also presented some of the latest research findings and the industry dynamics in this field.

Xi Wang, Academician and Director General of the Shanghai Institute of Microsystem and Information Technology (SIMIT) /Chinese Academy of Sciences (CAS) giving the first talk at the 2014 International RF-SOI Workshop.

Xi Wang, Academician and Director General of the Shanghai Institute of Microsystem and Information Technology (SIMIT) /Chinese Academy of Sciences (CAS) giving the first talk at the 2014 International RF-SOI Workshop.

 

Next, Handel Jones, CEO of IBS, gave a detailed analysis of the markets for smart phones and tablet PCs and other mobile consumer applications. These are strong drivers of the huge market opportunity and demand for chips based on RF-SOI technology. (Click here to view his presentation.)

 

(Courtesy: IBS)

(Courtesy: IBS)

This workshop also featured presentations by ST, GlobalFoundries and SMIC, as well as several important RF-SOI platform providers.

Mark Ireland, Vice President of Strategy and Business Development at the IBM Microelectronics Division, noted that that IBM first began offering RF-SOI manufacturing in 2006.  He explained the key role RF-SOI plays in redefining chips for mobile applications, where integration and performance are key. (Click here to view his presentation.)

Laura Formenti, Infrastructure and RF-SOI Business Unit Director at STMicroelectronics, gave a detailed analysis of RF-SOI. She covered the advantages of RF front-end integration and introduced ST’s H9SOI_FEM technology platform. (Click here to view her presentation.)

Paul Colestock, Sr. Director of Segment Marketing at GlobalFoundries shared specifics and the latest developments in the 130nm RF-SOI technology platform, UltraCMOS 10.

 

The room was full at the Shanghai RF-SOI Workshop 2014

The room was full at the Shanghai RF-SOI Workshop 2014

 

Herb Huang, Sr. Director Development, Technology R&D at SMIC, China’s largest foundry, addressed SOI in RF switches. He shared details on SOI NFETs for enhanced performance, and on CMOS MEMS RF filters. SOI CMOS will facilitate integration of switches (SW), power amplifiers (PA), envelope tracking (ET) and antenna tuning (AT) in SoCs. The foundry provides not only device-level processes but also support for high-performance system-in-package (SiP) solutions at the wafer level.

Professor Jean-Pierre Raskin of the Catholic University of Leuven (Belgium) and Bernard Aspar, General Manager of Soitec’s Communication & Power Business Unit presented detailed technical analyses of SOI substrates.  They covered the influence of substrates on RF signal integrity and the key role they play in improving RF performance thanks to the enhanced Signal Integrity (eSI™) High Resistivity SOI substrate.  (Click here to view the UCL presentation, and here to view the Soitec presentation.)

James Young, VP of Engineering, FES Si Platform Engineering at Skyworks focused on RF and wireless semiconductor design. In particular he addressed mobile phone design, including PA, ET and APT (Average Power Tracking). He gave performance comparisons and analysis for SOI/CMOS vs. GaAs devices.  (Click here to view the presentation.)

Dr. Yumin Lu, VP of the Shanghai Industrial μTechnology Research Institute Co.,Ltd. elaborated on how 4G wireless communications brings new challenges for RF front-end modules and components. RF-SOI has become a mainstream technology for antenna/switches. There is also significant potential for RF-SOI to make further inroads in applications such as tunable components (including antennas, PAs, filters/duplexers, etc.). (Click here to view the presentation.)

RFSOI_Shanghai14_RoundtableDiscussion

Roundtable Discussion at the 2014 International RF-SOI Workshop in Shanghai

The final panel discussion session on the “China RF market” started a lively debate. Topics included the specificities and drivers of the China RF market, Chinese foundry capacity, the RF-SOI supply chain, RF front-end module (FEM) system packaging and system integration trends, and LTE and WiFi common platforms on RF-SOI substrates.  Audience members had questions about device design. The need for the industry to establish a broader ecosystem was a common theme.

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Editor’s note: This article was first posted in Chinese at Shanghai Institute of Micro-Technology Industry Views. You can see the original hereMany thanks to Xi Wang, Academician and Director General of the Shanghai Institute of Microsystem and Information Technology (SIMIT) /Chinese Academy of Sciences (CAS) for his permission to translate/adapt and reprint it here in ASN.

SOI-3D-SubVt (S3S): three central technologies for tomorrow’s mainstream applications

ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm.

We learned all this and much more during the very successful 2014 IEEE S3S Conference.

The conference’s 40th edition (first created as the IEEE SOS technology workshop in 1975) was held in San Francisco Oct. 6-9. Dedicated to central technologies for tomorrow’s mainstream applications, the event boasted nearly 80 papers presented over 3 days covering conception, design, simulation, process and characterization of devices and circuits.

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Many of the talks we heard made it very clear that the Internet-of-Things will be the next big market growth segment. It will be enabled by extremely energy-efficient and low-cost technologies in the field of RF-communications, sensors and both embedded and cloud computing. The program of the conference was very well designed to tackle these topics, starting with the short courses on Energy Efficiency and Monolithic 3D, an RF fundamentals & applications class, a MEMS hot topic session and a strong focus on ultra-low power throughout the SubVt sessions.

(Photo credit: Justin Lloyd)

S3S Conference Poster & reception session. (Photo credit: Justin Lloyd)

 The interest of the participants could be seen through an increase in Short Course and Fundamentals Class participation (+20%) compared to last year.

 The companies working in the field of RF communications and mobile chips were well represented, including attendees and presenters coming from Broadcom, MediaTek, Murata, Newlans, Qualcomm, RFMD, Skyworks and TowerJazz.

 

Sub-Threshold Microelectronics

The SubVT portion of the conference featured an extremely strong suite of papers on advancements in subthreshold circuit design including ultra-low-voltage microprocessors, FPGAs, and analog circuits. Additionally, there were sessions on technologies which enable very low voltage computation, such as radiation testing during subthreshold operation, and efficient energy-harvesting devices to allow indefinite operation of IoT systems. A number of talks explored the future of ultra low voltage computing, presenting results from emerging technologies such as Spin Torque Transfer devices and TFETs.

3D Integration

The 3D integration track keeps growing in the conference and is strongly focused on monolithic 3D. A dedicated full day short course was offered again this year, as well as two joint sessions featuring several papers on process integration, design, precision alignment bonders and more. Progress is being made and a lot of interest in this technology is being generated (See the EE Times article).

Key Fully-Depleted SOI Technical results

Planar Fully-Depleted SOI technologies were well represented again this year, in both SOI and Sub-Vt parallel sessions. A full session was also dedicated to FinFETs.

STMicroelectronics and CEA-Leti gave us a wealth of information on:

  • From "Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology" in the S3S '14 "Energy Efficiency" short course by P. Flatresse (Source: STMicroelectronics)

    From “Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology” in the S3S ’14 “Energy Efficiency” short course by P. Flatresse (Source: STMicroelectronics)

    How to improve your circuit’s efficiency by co-optimizing Vdd, poly-bias and back-gate voltage simultaneously during the circuit design. Picking the correct optimization vector enables you to gain more than 2X in speed or up to 5X in power compared to the non-optimized circuit. (P. Flatresse, “Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology” in the “Energy Efficiency” short course). In the same presentation we saw how going to a single-well configuration can help further reduce SRAM’s VMin by 70mV (see graph to the right).

  •  How to use FMAX tracking to maintain optimal Vdd, VBB values during operation. This shows how you can take advantage of both Vdd and VBB dynamic modulation to maintain your circuit’s best performance when external conditions (e.g. temperature, supply voltage…) vary. (E. Beigné, “FDSOI Circuit Design for a Better Energy Efficiency”).

The latest updates on 14nm technology, including an additional 2ps/stage RO delay reduction since the 2014 VLSI results shown last June. This means ROs running faster than 8ps/stage at 10nA/stage of static leakage. The key elements for the 10nm node (sSOI, thinner BOX, replacement gate, next gen. ID-RSD) where also discussed. (M. Haond, “14nm UTBB FD-SOI Technology”).

In the past year we witnessed the foundry announcements for FD-SOI technology offering. Global Foundries very clearly re-stated their interest in the FD-SOI technology, claiming that 28FD-SOI is a good technology for cost sensitive mobile applications, with the cost of 28LP and the performance of 28HPP. However, GF favors a flavor of FD-SOI technology they call Advanced ET-SOI, with similar performance to 20LPM at a reduced cost.

More than An Order of Magnitude Energy Improvement of

From S3S 2014 Best Paper, “More than An Order of Magnitude Energy Improvement of FPGA by Combining 0.4V Operation and Multi-Vt Optimization of 20k Body Bias Domains” (AIST)

The IEEE S3S Conference Best Paper Award went to Hanpei Koike and co-authors from the National Institute of AIST, for their paper entitled “More than An Order of Magnitude Energy Improvement of FPGA by Combining 0.4V Operation and Multi-Vt Optimization of 20k Body Bias Domains,” presented in the SubVT part of the conference. In this work, an FPGA was fabricated in the AIST SOTB (Si On Thin BOX — which is another name for FD-SOI) process, and demonstrated successful operation down to voltages at and below the minimum energy point of the circuit. A 13x reduction in Power-Delay-Product over conventional 1.2V operation was achieved through a combination of low voltage operation and flexible body-biasing, enabled by the very thin BOX.

On the FinFET side, T.B. Hook (IBM) presented a direct comparison of “SOI FinFET versus Bulk FinFET for 10nm and below”, based on silicon data. This is a very unique work in the sense that both technologies are being developed and optimized by the same teams, in the same fab, with the same ground rules, which enables a real apple-to-apple comparison. SOI comes out a better technology in terms of Fin height control (better performance and ION variability), VT mismatch (lower VMin), output conductance (better analog and low voltage perf.) and reliability. Though external stressors are expected to be more efficient in Bulk FinFETs, mobility measurements are only 10% lower for SOI PFETs and are actually 40% higher for SOI NFETs, because of the absence of doping. The devices’ thermal resistance is higher on SOI, though bulk FinFETs are not as immune to self-heating as planar bulk. Both technologies are still competitive down to the 10nm node, but looking forward, bulk’s advantages will be rendered moot by the introduction of high mobility materials and dimensions shrinking, while SOI advantages will keep getting larger.

Experimental SOI vs. Bulk FinFET comparison showing 50% higher VT variability on bulk (grey dots on top graph) as well as mobility difference (lower graphs).

Experimental SOI vs. Bulk FinFET comparison showing 50% higher VT variability on bulk (grey dots on top graph) as well as mobility difference (lower graphs).

FinFET_SOI_IBM_S3S14_Mobility_1

Join the conference in 2015!

Next year, the S3S Conference will be held October 5-8, at the DoubleTree by Hilton Sonoma Wine Country Hotel, Rohnert Park, California.

The organizing committee is looking forward to seeing you there!

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Steven A. Vitale is an Assistant Group Leader in the Quantum Information and Integrated Nanosystems Group at MIT Lincoln Laboratory.  He received his B.S. in Chemical Engineering from Johns Hopkins University and Ph.D. in Chemical Engineering from MIT.  Steven’s current research focuses on developing a fully-depleted silicon-on-insulator (FDSOI) ultra-low-power microelectronics technology for energy-starved systems such as space-based systems and implantable biomedical devices.  Prior to joining MIT-LL, Steven was a member of the Silicon Technology Development group at Texas Instruments where he developed advanced gate etch processes. He has published 26 refereed journal articles and holds 5 patents related to semiconductor processing. From 2011 to 2012 Steven was the General Chair of the IEEE Subthreshold Microelectronics Conference, and is on the Executive Committees of the AVS Plasma Science and Technology Division, the AVS Electronic Materials and Processing Division, and the IEEE S3S Conference.

Frederic Allibert received his MS degree from the National Institute for Applied Sciences (INSA, Lyon, France) in 1997 and his PhD from Grenoble Polytechnic’s Institute (INPG) in 2003, focusing on the electrical characterization of Unibond wafers and the study of advanced device architectures such as planar double-gate and 4-gate transistors.  He was a visiting scientist at KAIST (Taejon, Korea) in 1998 and joined Soitec in 1999.  As an R&D scientist, he implemented SOI-specific electrical measurement techniques (for thin films, multi-layers, high resistivity) and supported the development of products and technologies targeting various applications, including FD-SOI, RF, imagers, and high-mobility materials.  As Soitec’s assignee at the Albany Nanotech Center since 2011, his focus is on substrate technologies for advanced nodes.  He has authored or co-authored over 50 papers and holds over 10 patents.

 

 

*RO = ring oscillator

 

 

FD-SOI Front and Center at Very Successful Semicon Europa

An ST key ring sporting their new FD-SOI logo (Semicon Europa 2014)

An ST key ring sporting their new FD-SOI logo (Semicon Europa 2014)

Yes, GlobalFoundries is hot on FD-SOI. Yes, Qualcomm’s interested in it for IoT. Yes, ST’s got more amazing low-power FD-SOI results. These are just some of the highlights that came out of the Low Power Conference during Semicon Europa in Grenoble, France (7-9 October 2014).

This was Semicon Europa’s first time in Grenoble, the heart of FD-SOI country, and it was a terrific success. There was a ton of energy, a raft of very well-attended conferences, and vendors on the show floor were clearly pumped up by the high-quality lead generation they reported.  Attendance (over 6K visitors) and floor space were both up (>40%). Highlights follow.

 Low Power Conference

It was standing-room only for ST COO Jean-Marc Chery’s keynote. In addition to apps in FD-SOI for mobile, consumer and network infrastructure, he was very bullish on automotive, noting that this is a place FinFETs can’t go.  He indicates a major announcement is impending.

 

ST slide on an automotive app on FD-SOI (Semicon Europa 2014 Low Power Conference)

ST slide on an automotive app on FD-SOI (Semicon Europa 2014 Low Power Conference)

Next up, Manfred Horstmann, Director of Products & Integration for GlobalFoundries in Dresden said that FD-SOI would be their focus for the next few years. They’re also calling it ET-SOI (for extremely thin), and he said it’s the right solution for SOCs, especially with back biasing. Plus, it’s good for the fab because they can leverage their existing tool park. Asked if they were seeing interest, he said yes. Asked if they have customers lined up, he said yes. So watch this space – there’ll be news soon!

GlobalFoundries slide on the FD-SOI value proposition (Semicon Europa 2014 Low Power Conference)

GlobalFoundries slide on the FD-SOI value proposition (Semicon Europa 2014 Low Power Conference)

ST Fellow and FD-SOI guru Thomas Skotnicki gave an excellent talk  — he’s been ST’s champion of the concept for 26 years, and noted that the breakthrough by Soitec a few years ago in making the ultrathin SOI wafers with ultrathin box made industrialization a reality.  He sees it having a very long life, with monolithic 3D stacking replacing scaling.

The Qualcomm Technologies talk by Senior Program Manager Mustafa Badaroglu was largely about FinFET challenges, and while he observing that SOI was the best solution for leakage, cost concerns remain. With respect to FD-SOI, however, he did note that 28nm is very attractive for IoT apps. Interesting, too, that he stayed for all the other presentations and asked a lot of incisive questions about FD-SOI.

Fabien Clermidy, Sr. Expert at Leti, looked at low-power multiprocessing for markets spanning embedded through servers.  His team’s working at full bore on the Euroserver project, which leverages FD-SOI, ARM cores, monolithic 3D – you name it. He also gave some impressive details on the FRISBEE DSP, which operates from 0.3V to 1.2V, getting performance of 200MHz at the low end of the power supply and 2.7 GHz at the high end.

Leti slide on the Euroserver (Semicon Europa 2014 Low Power Conference)

Leti slide on the Euroserver (Semicon Europa 2014 Low Power Conference)

Shiro Kamohara, Chief Engineer of the Low Power  Electronics Association & Project (aka LEAP) and Renesas gave a compelling talk about their vision of FD-SOI, which they call SOTB (for silicon-on-thin-box) for IoT.  They see lots of possibilities, including for getting more life out of older nodes and fabs. They have even demonstrated a 32 bit CPU on 65nm SOTB with back bias that operates eternally (that’s right!) with ambient indoor light – clearly something to watch for.

LEAP slide on SOTB (aka FD-SOI) for IoT (Semicon Europa 2014 Low Power Conference)

LEAP slide on SOTB (aka FD-SOI) for IoT (Semicon Europa 2014 Low Power Conference)

A talk by Soitec CTO, Carlos Mazure focused on the SOI wafers for current and future generations of FD-SOI and FinFETs, as well as for RF. He noted that RF-SOI wafers for switches and antenna tuners enjoy a >80% market share.  For 28nm, he cited VeriSilicon’s figures from the recent Shanghai FD-SOI forum that indicated FD-SOI savings of 19% in area, 71% in standby power and 58% in power over bulk.

A fascinating talk by Handel Jones of IBS (see his ASN articles here) looked at IoT. We need to be thinking about billions of chips – not millions – at under $10, he said.  He sees the industry at a tipping point now, with more local intelligence coming. IBS is convinced that FD-SOI is the best technology for IoT apps, in large part because of memory driving cost, size and power consumption requirements.

Power (high & smart), power (very low), 3D and more

During the Semicon Europa Power Electronics conference, Soitec BizDev Manager Arnaud Rigny looked at high voltage devices on SOI, in “smart substrates for smart power”.  While these wafer substrates can be either “thick” or “thin” SOI (referring to the top layer of silicon), smart power (which includes analog, logic & power) typically uses a relatively thin SOI. However, in this case the top silicon uniformity needs to be greater. He said it’s a good growth area for Soitec, which is seeing an uptick of 20% in thin SOI wafers for smart power. The biggest market there is automotive.

Soitec slide on SOI for smart power (Semicon Europa 2014 Power Electronics Conference)

Soitec slide on SOI for smart power (Semicon Europa 2014 Power Electronics Conference)

There was a great turnout for Leti’s talk by Senior Scientist Claire Fenouillet-Béranger in the TechArena showing their monolithic 3D integration scheme. They’re reporting savings in area of 55%, performance of 25% and power of 12%.  Look for more breakthroughs in their paper at IEDM this December, she said.

Leti’s presentation on monolithic 3D integration (Semicon Europa 2014 Tech Arena)

Leti’s presentation on monolithic 3D integration (Semicon Europa 2014 Tech Arena)

And finally, out on the show floor, in addition to their great FD-SOI keying (see above), ST had a cool – make that freezing – demo showing the effectiveness of back biasing in FD-SOI at very low power and very, very cold temperatures. Officially titled “Temperature self-compensation on 32b RISC FDSOI28 thru dynamic body biasing down to 0.35V”, we saw the chip could run stably at 20MHz with a supply voltage of just 0.45V – that’s amazing in itself – but that it should maintain stability at -22oC is absolutely phenomenal. Body biasing dynamically compensates for the temperature fluctuations. This points up just how important FD-SOI will be for ultra-low power IoT, and in this case for things like medical apps. (If you’re very patient, you can watch this blogger’s attempt to capture the ST demo on her iPhone here.)

ST’s FD-SOI demo (Semicon Europa 2014)

ST’s FD-SOI demo (Semicon Europa 2014)

So it was a great show – kudos to the folks at Semi.  Next year it will be in Dresden, and alternate between Grenoble and Dresden from then on. And now we know that interesting things are promised for FDSOI in Dresden, we’ll certainly look forward to 2015.

 

Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct)

S3Sheader

(For best rates, register by September 18th.)

The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco.

Photo Credit: Catherine Allibert

Photo Credit: Catherine Allibert

Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S conference was successful by any measurement. The first year of the new conference leading-edge experts from 3D Integration, Sub-threshold Microelectronics and SOI fields gathered and we established a world class international venue to present, learn and debate about these exciting topics. The overall participation at the first year of the new conference grew by over 50%, and the overall quality and quantity of the technical content grew even more.

This year we are looking forward to continuing to enhance the content of the 2014 S3S Conference.

 

Short courses: Monolithic 3D & Power-Efficient Chip Tech

On Monday, Oct. 6 we will feature two Short Courses that will run in parallel. Short courses are an educational venue where newcomers can gain overview and generalists can learn more details about new and timely topics.

The short course on Monolithic 3D will be a full day deep dive into the topic of three-dimensional integration wherein the vertical connectivity is compatible with the horizontal connectivity (10,000x better than TSV). Already there are extremely successful examples of monolithic 3D Flash Memory. Looking beyond this initial application, we will explore the application of monolithic 3D to alternate memories like RRAM, CMOS systems with silicon and other channel materials like III V. In addition, a significant portion of the short course will be dedicated to the exciting opportunity of Monolithic 3D in the context of CMOS Logic.

The other short course we will offer this year is entitled Power Efficient Chip Technology. This short course will address several key aspects of power-efficiency including low power transistors and circuits. The course will also review in detail the impact of design and architecture on the energy-efficiency of systems. The short course chairs as well as the instructors are world class leading experts from the most prestigious industry and academic institutions.

 

Conference program

The regular conference sessions will start on Tuesday Oct. 7 with the plenary session, which will feature presentations from Wall Street (Morgan Stanley Investment Banking), Microsoft and MediaTek. After the plenary session we will hear invited talks and this year’s selection of outstanding papers from international researchers from top companies and universities. The most up to date results will be shared. Audience questions and one on one interaction with presenters is encouraged.

Back by popular demand we will have 2 Hot Topics Sessions this year. The first Hot Topic Session is scheduled for Tuesday Oct. 7th and will feature exciting 3DI topics. The other Hot Topics session is scheduled for Thursday Oct 9 and will showcase new and exciting work in the area of MEMS.

Our unique poster session and reception format will have a short presentation by the authors followed by one on one interaction to review details of the poster with the audience, in a friendly atmosphere, around a drink. Last year we had regular posters as well as several invited posters with very high quality content and we anticipate this year’s poster session to be even better than last years.

We are offering a choice of two different fundamentals classes on Wednesday afternoon. One of the Fundamentals classes will focus on Robust Design of Subthreshold Digital and Mixed Circuits, with tutorials by the worlds leading experts in this field. The SOI fundamentals course is focused on RF SOI Technology Fundamentals and Applications.

Our technical content is detailed on our program webpage.

 

Panel discussions, cookout & more

Keeping in line with tradition, on Wednesday night we will have a hearty cook out with delicious food and drink followed by the Panel Session entitled Cost and Benefit of Scaling Beyond 14nm. Panel speakers from financial, semiconductor equipment, technology, and academic research institutions will gather along with the audience to debate this timely topic. Although Thursday is the last day of the conference we will have stimulating presentations on novel devices, energy harvesting, radiation effects along with the MEMS Hot Topic Session and Late News Session. As always we will finish the conference with the award ceremony for the best papers.

SFstreetsignOur conference has a long tradition of attracting presenters and audience members from the most prestigious research, technology and academic institutions from around the world. There are many social events at the S3S Conference as well as quiet time where ideas are discussed and challenged off line and people from various fields can learn more about other fields of interest from leading experts.

The conference also offers many opportunities for networking with people inside and also outside ones area. The venue this year is San Francisco. We chose this location to attract the regions leading experts from Academia and Industry. If you have free time we encourage you to explore San Francisco which is famous for a multitude of cultural and culinary opportunities.

Please take a moment to learn more about our conference by browsing our website or downloading our advance program.

To take full advantage of this outstanding event, register before September 18!

Special hotel rates are also available from the dedicated hotel registration page.

The committee and I look forward to seeing you in San Fransisco.

– Bruce Doris, S3S General Chair

 Photo Credit: Catherine Allibert

Photo Credit: Catherine Allibert

More FD-SOI myth-busting, courtesy semiwiki

In his recent piece, A couple of misconceptions about FD-SOI (3 September 2014), semiwiki blogger and IP expert Eric Esteve corrects some assertions surfacing about FD-SOI.  He reminds designers that to really benefit from FD-SOI, you want to leverage body-biasing. He explains how ST has automated the IP conversion process so it takes about half the time you’d normally expect. He also advocates FD-SOI for wearables and smartphones, as it provides both performance advantages and power savings.

Engaging Kleinman (ex-GF/Xilinx) piece on LinkedIn Advocates for 28nm FD-SOI

A thoroughly engaging and amusing LinkedIn Pulse piece by Bruce Kleinman comes down firmly on the side of 28nm FD-SOI.  Entitled 28nm: Home Improvements (posted 13 August 2014), it’s subtitled, “Welcome to 28nm! Make yourself comfortable, we’re going to be here for awhile.” He says (among lots of other things, including astute observations about 3D), “…in my book 28nm FD-SOI offers very similar performance/power characteristics to 20nm bulk silicon.” Kleinman’s currently SVP at HMicro, which is doing SOC solutions for demanding wireless apps and IoT.  He’s clearly got the street creds, arriving there by way of upper management at GlobalFoundries, Xilinx, HP, etc., having started out with a Stanford MSEE.  A good read – recommended.

Murata to Acquire RF-SOI Pioneer Peregrine Semi

Murata and Peregrine Semiconductor have entered into a definitive agreement under which Murata will acquire all outstanding shares of Peregrine not owned by Murata (read full press release here). Peregrine will become a wholly owned subsidiary of Murata and continue with its current business model of solving the world’s toughest RF challenges. Peregrine supplies many wireless markets, including: smartphones, test & measurement, automotive, public safety radio and wireless infrastructure. Peregrine will also provide Murata with a strong portfolio of Intellectual Property Rights (IPR) covering the entire RF-SOI front-end.

“Murata is the world’s leading RF module and filter provider, and we have benefited from our many years of partnership with them. The combination of Murata’s leading products with Peregrine’s leading-edge SOI products will position us to compete aggressively in our chosen markets,” said Jim Cable, PhD, Chairman and CEO of Peregrine Semiconductor. “As part of the Murata team, we will be able to expand our existing partnership and speed the industry’s transition to an integrated, all-CMOS RF front-end. We remain committed to providing leading solutions to customers in all our current markets. We have huge respect for Murata’s capabilities, and look forward to jointly accomplishing great things.”

ST presents silicon R&D results on hafnium memory technology for FD-SOI MCUs

Peter Clark at Electronics360 wrote about a recent presentation by an STMicroelectronics research team using hafnium oxide for non-volatile embedded memory. (Read the full article here.) The results were given at a Leti memory workshop in June 2014. The team presented, “… results for a 16-kbit OxRAM test chip implemented in 28nm high-k metal gate process.” The project is under the aegis of a French government funded program for “…the development of magnetic RAM and resistive RAM embedded memory options for the 28nm fully-depleted silicon-on-insulator (FDSOI) manufacturing process and subsequent generations.” MCU tape-out is scheduled for the end of 2014.

ST’s Integrated RF-SOI for Front-End Modules: Why Designers Like It

RF-SOI is good for more than integrating RF switches.  Other key functions typically found inside RF Front-End Modules (FEM) like power amplifiers (PA), RF Energy Management, low-noise amplifiers (LNA), and passives also benefit from integration.

Last year, ST announced a monolithic approach with a new RF-SOI process called H9SOI_FEM that allows the integration of all those key FEM functions.

This process is an evolution of the H9SOI SOI process, a groundbreaking technology introduced by ST in 2008 and subsequently used by customers to produce more than 400 million RF switches for mobile phones and Wi-Fi applications. Building on that experience, ST optimized H9SOI for creating integrated front-end modules, resulting in the H9SOI_FEM offering a Factor of Merit (FoM) for switches 2x better than the previous H9SOI generation.

The new process greatly reduces the size of multi-band radios for 4G and other high-speed wireless connections.

 

Integration drivers and challenges

The market for 4G-LTE devices based on the RF-SOI process is growing at a remarkable 60% annual rate. Driving this progress are phone makers and operators wanting to speed-up and minimize reference-design variants, which require an RF front-end able to support several tens of bands. The required qualities of flexibility, tune-ability, and integration rely on the wide usage of RF-SOI processes that provide good RF switch performance (Ron, Coff) whereas standard bulk processes deliver less robust isolation (poor Coff).

 

 ST_RFSOI_switch_1Figure 1. An RF switch designed with ST’s RF-SOI achieves 3G and 4G standard specifications.

 

 

 

 

 

 

 

 

 

 

So far, the biggest RF-SOI challenge has been to minimize the performance gap versus traditional JFet GaAs and Silicon-on-Sapphire (SoS) processes. In the last few years, we have seen it become possible to reduce the figure of Merit (FoM =Ron*Coff) by a factor of two with RF-SOI technologies. As a consequence, it’s now possible to get 0.5 dB Insertion Loss (IL) @2 GHz for a single-path 10-throws RF switch.

Meeting the challenging requirements of LTE has entailed a specific focus on linearity to improve IMD parameters and avoid the use of additional filters.  In this way, very low harmonics (H2= -80 dBm and H3=-75 dBm) have been reached with Pin=26 dBm@2 GHz. Based on these positive results, RF-SOI is now a mainstream solution and the most effective way to produce an RF switch.

 

Integrating the PA, LNA and passives

With an RF FEM, a key component to integrate is the Power Amplifier (PA). The Power Added Efficiency (PAE) is a figure of merit for PAs. So far, the weakness of the bulk CMOS PA has been the reduced PAE versus GaAs. Now, a specific n-type Lateral Extended Drain MOS (nLEDMOS) RF-SOI device has enabled the realization of excellent performance such as PAE > 80% @ 2GHz.

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Figure 2. ST RF-SOI 4mm nLEDMOS load-pull measurement, giving maxPAE at 80% (blue line) and max DEff above 85% (red line) at 12dB gain (green line) @1.9GHz.

 

 

 

 

 

 

 

On top of reliability and performance, the benefits of nLEDMOS are ease of design and a more secure approach because the component can handle more than 12V. In addition to a high PAE, other challenges have been addressed. Improved linearity, for example, has a significant impact on the Adjacent Channel Leakage Power Ratio (ACLR), and the need to embed the output matching network with low insertion losses. pLEDMOS can also be very useful for RF power management devices including Power Tracking (PT) and Envelop Tracking (ET).

 

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Figure 3. A 3G Band I power amplifier, using an nLEDMOS device, embedded in an LGA package, demonstrates RF-SOI technology’s ability to reach 3G specifications.

 

 

 

 

 

 

 

 

Another RF-SOI target is Low Noise Amplifier (LNA) integration using a smaller lithography (0.13µm) transistor. It has just been demonstrated that 802.11ac requirements are fully achieved with 1.5 dB NF, 12 dB gain, and 7 dBm IP3. The other key blocks available with Wi-Fi modules, power-amplifiers, and switches can also be fully integrated using existing RF-SOI devices.

 

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Figure 4. A 5 GHz LNA suitable for 802.11ac WiFi applications.

 

 

 

 

 

 

 

 

 

 

Moreover, there is a need to embed filtering functions using passives. Then, thanks to a thick copper back-end and substrate resistivity > 1Kohmcm, key functions like a diplexer, low-pass/band-pass filters for GSM, and couplers can easily be integrated. Pcell for coils are also available to speed-up the design phase.

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Figure 5. A GSM/DCS diplexer, designed in ST’s RF-SOI CMOS technology, achieves a very compact form factor.

 

 

 

 

Increased manufacturing capacity, shorter cycles

H9SOI_FEM is suitable both for devices targeting the low end of the market, where low cost and extensive integration are crucial, as well as the high-end smartphone segment. High-end products typically require a combination of many frequency bands to support not only 2G, 3G and 4G standards, but also various other wireless connectivity standards such as Bluetooth, Wi-Fi, GPS and NFC (Near-Field Communication) for contactless payments.

These are demanding, volatile, high-volume markets. Therefore, ST has also invested to expand our manufacturing capacity. We developed a simplified process flow with fewer masks and fewer process steps to enable extremely short overall lead-times and supply flexibility.  Products designed by our customers leveraging the H9SOI_FEM process are now ramping in volume.   With all these factors in place, we’re pleased to report that the response from our customers has been extremely favorable.

Further detailed information on H9SOI_FEM can be found on ST’s website (click here).

Peregrine and RFMD Settle All Outstanding RF-SOI Litigation

In RF-SOI news, Peregrine and RFMD announced that they have settled all outstanding claims between the companies (read press release here). The two companies have entered into patent cross licenses and have agreed to dismiss all related litigation.

“We are pleased that we have reached agreement with RF Micro Devices and resolved all of our outstanding litigation under terms that recognize Peregrine’s unique role in the invention and commercialization of RF SOI technology,” said Jim Cable, CEO of Peregrine Semiconductor.  “This agreement provides validation for the many ways in which Peregrine continues to expand the industry’s technological frontiers through both our inventions and commercial products. We look forward to continuing to solve our customers’ and partners’ toughest RF challenges.”

Bob Bruggeworth, president and CEO of RFMD, said, “We are very pleased to reach an agreement with Peregrine that recognizes the value of their patents and their contribution to the development of RF SOI. The signing of this patent cross‐license agreement allows RFMD to focus 100% on building the industry’s  leading portfolio of RF solutions, making this agreement very positive for both our company and our customers.”