• Soitec has announced the acquisition of TraciT Technologies. A CEA-Léti spin-off, TraciT specializes in thin-film layer transfer technologies that leverage molecular adhesion and mechanical and chemical thinning processes for MEMS and power-circuit production. The technology is complementary to Smart Cut,™ and enables Soitec to enter new electronic markets, thanks to fully-processed electronic circuits transfer technology, which has short-term applications for wafer-level packaging.
The KORRIGAN program will provide a forum for suppliers and system houses to confirm new approaches.
KORRIGAN is a very important program in terms of GaN material and device development, giving suppliers the opportunity to demonstrate technology and products to European defense companies. This complements cooperation and business relations with Asian or US based customers who already expressed interest in those new generations of solutions. Read More
Joint effort focuses on perfecting the wet-etch process used to optimize and speed germanium removal during sSOI volume production
Soitec and SEZ have initiated a joint development program intended to speed the industrialization of next-generation strained silicon-on-insulator (sSOI) substrates. The goal is to develop new wet-etch processes designed to optimize total germanium removal in sSOI manufacturing. In the sSOI Smart Cut™ process, selectively etching off the germanium template, which is used only to induce the “strain” in the active silicon layer, is a critical step. Read More
Smart Cut™ enables innovative substrate solutions
GaN HEMT technology holds enormous promise for increasing the power of commercial RF applications. However, challenges both technological and economic remain to be resolved before GaN can realize its full potential beyond the very high-end niche. Read More
Dr. Yoshimi reviews some recent approaches to strained SOI implementation
Implementing strain into the channel of MOSFETs has become mainstream technology for high-performance CMOS-FETs. Process induced uniaxial stress is being used today to boost carrier mobilities of sub-µm devices and thus improve IC performance. Read More
The inventor of Smart Cut technology, Dr. Bruel reflects on its impact for the industry.
I knew a time when it was very common to encounter people who didn’t believe in the future of SOI technology, when people thought that only bulk silicon technologies would solve microelectronics’ new challenges. Read More
Financing approved for new III-V program
The first phase of OPTIMUM, a new III-V research project lead by Thales Communications France (TCF) and partners UMS, OMMIC and Picogiga International, has recently been approved and financed. There are four sub-sections within the pro-ject. The first focuses on innovative III-V materials and technologies, in particular the optimization of GaAs substrates and the use of Smart Cut technology in future materials such as GaN and InP. Other sections focus on basic technologies such as packaging, as well as components and applications. With synergies established between the major players, the consortium expects to facilitate an expanded, world-class industrial and research pole of excellence in III-V based microelectronics and optoelectronics for the greater Paris region. •