Tag Archive SOI

Fab Floor Tip: Running SOI in RTP
Posted date : Dec 7, 2005

A quick guide to successful rapid thermal processing of SOI wafers Some engineers have indicated that they encounter challenges when running SOI

Achieving High Throughput Inspection of Multiple SOI Wafers
Posted date : Dec 7, 2005

Historically, chipmakers conducting incoming quality control (IQC) on SOI wafers used for advanced logic devices are challenged in inspecting the

Soitec and SEZ Collaborate to Speed Industrialization of sSOI
Posted date : Dec 7, 2005

Joint effort focuses on perfecting the wet-etch process used to optimize and speed germanium removal during sSOI volume production   Soite

NIST Nanowire Transistors on SOI
Posted date : Dec 7, 2005

New design simplifies processing and on/off switching Using SOI as the substrate, researchers at the National Institute of Standards and Technol

More and More Strain
Posted date : Dec 7, 2005

Dr. Yoshimi reviews some recent approaches to strained SOI implementation Implementing strain into the channel of MOSFETs has become m

SOI and sSOI Address MPU Clock Speed Challenge
Posted date : Jul 11, 2005

IC makers need both local and global strained SOI to win the GHz race. At the device level, the switching speed of MOS

On the Smart Cut™ Frontier
Posted date : Jul 11, 2005

The inventor of Smart Cut technology, Dr. Bruel reflects on its impact for the industry. I knew a time when it was very common to e

MEDEA+ 2T101: sSOI for High-Performance ICs
Posted date : Jul 11, 2005

The objective is to provide an industrial source of large diameter strained SOI wafers within 3 years. A “Phase 2” MEDEA+ project,

New Edition of SOI Book by J.-P. Colinge
Posted date : Jul 11, 2005

Silicon-on-Insulator Technology: Materials to VLSI is now available from Springer. The third edition of Professor Jean-Pierre Colin

10 Years – Already?
Posted date : Jul 11, 2005

One of the world’s leading SOI experts considers Smart Cut innovations and future potential. I remember a meeting with a PhD stud