Tag Archive Soitec

What’s After Silicon?
Posted date : Apr 6, 2006

For each technology node, those in the substrate world have to be ready with options years in

Strained Silicon on Insulator: the Wafer Solution for Low-Power and High-Performance Devices
Posted date : Apr 6, 2006

sSOI is on-track for high-volume manufacturing at the 45nm node. The end of conventional scaling is a topic that has generated disc

Fab Floor Tip: Running SOI in RTP
Posted date : Dec 7, 2005

A quick guide to successful rapid thermal processing of SOI wafers Some engineers have indicated that they encounter challenges when running SOI

Soitec and SEZ Collaborate to Speed Industrialization of sSOI
Posted date : Dec 7, 2005

Joint effort focuses on perfecting the wet-etch process used to optimize and speed germanium removal during sSOI volume production   Soite

Soitec President Elected to SEMI Board
Posted date : Dec 7, 2005

Auberton-Hervé joins other prominent industry leaders in representing the interests of material suppliers and equipment manufacturers  

New Options for GaN RF
Posted date : Dec 7, 2005

Smart Cut™ enables innovative substrate solutions GaN HEMT technology holds enormous promise for increasing the power of commercial RF a

More and More Strain
Posted date : Dec 7, 2005

Dr. Yoshimi reviews some recent approaches to strained SOI implementation Implementing strain into the channel of MOSFETs has become m

SOI and sSOI Address MPU Clock Speed Challenge
Posted date : Jul 11, 2005

IC makers need both local and global strained SOI to win the GHz race. At the device level, the switching speed of MOS

STRAINED SOI
Posted date : Jul 11, 2005

APRIL 2005 - FREESCALE AND SOITEC ACHIEVE 70- PERCENT IMPROVEMENT IN ELECTRON MOBILITY USING

Substrate strategies for high-performance and low-power applications at 45 nm
Posted date : Jul 11, 2005

Two distinct technical strategies for advanced substrates will mark the 45nm node. One will be focused on high performance, the other driven by s