The MCU at the heart of Sony’s new smart-sensing SPRESENSE™ for IoT is built on FD-SOI. Why? Low operating voltage and low power consumption, of course! Sony’s got two cool new products going on sale in July 2018: the SPRESENCE main and extension boards for IoT applications, equipped with a smart-sensing processor (read the full press release here). A CXD5602PWBCAM1 camera board for sensing cameras will go on sale in August. All were on display at the SF Maker Fair ’18, where they were an instant hit.
Spresense is powered by Sony’s FDSOI-based CXD5602 MCU (ARM Cortex-M4F × 6 cores), with a clock speed up to 156 MHz. The main board utilizes a multi-CPU structure equipped with Sony’s state-of-the-art GNSS (Global Navigation Satellite System – which they talked about at the most recent SOI Symposiums in SF and Tokyo) receiver. A variety of systems for diverse applications, including drones, smart speakers, sensing cameras and other IoT devices, can be built by combining these boards and developing the relevant applications.
The new board can be used to control a drone, for example, using GPS positioning technology and a high-performance processor, voice-controlled smart speakers, low-power consumption sensing cameras and other IoT devices, etc. It can also be combined with various sensors for use in systems that detect errors in production lines on the factory floor.
“The ecosystem is ready. The focus is now on applications and products.” And with those words, SOI Consortium Executive Director Carlos Mazure opened the annual Silicon Valley SOI Symposium. As promised, the day was packed with presentations about products on FD-SOI – some from big players like NXP and Sony, some from names new to the FD-SOI ecosystem like Audi and Airbus, and some from start-ups just getting into the game.
The event got excellent coverage in EETimes/EDN – including in their editions across the globe in China, Japan, Taiwan, India and more. Samsung, GF Ramp FD-SOI, heralded the headlines.
It was a full day of excellent presentations. In this post, I’ll chronicle the morning presentations. The next post(s) will cover the afternoon session. Note that as of this writing, the ppts are not yet posted on the SOI Consortium website, but many will be. Keep checking back under the Events tab, and look under “past Events”.
As semiwiki noted a few years back, Andes Technology is “…the biggest microprocessor IP company you’ve never heard of.” Based in Taiwan, Mediatek is one of their big customers; they’ve got a strong client base across Asia/Pacific, and are now making inroads into North America. Last year they announced with GF their 32-bit CPU IP cores had been implemented on GF’s 22FDX® FD-SOI technology.
In his symposium keynote, CEO Frankwell Lin said that in the test chip they’re doing with GF and Invecus, they’re seeing a 70% power savings compared with what they’d gotten in 28ULP. Their newest products are the N25 32bit and NX25 64bit RISC-V based cores, and in July they’ll announce a core that runs on Linux.
“With FD-SOI we’re enabling the future of embedded processing,” the always-quotable (and keynote speaker) NXP VP/GM Ron Martino told us. NXP’s i.MX7ULP, i.MX8, i.MX8X and i.MXRT are all FD-SOI based. They all share fundamental building blocks, so NXP can build platforms, scale and re-use IP. “It’s better than any technology I’ve worked on in my 30 years in the industry,” he said.
They’re seeing much higher performance with on-chip flash. And the RT “crossover” processor boasts 3x higher computing performance than today’s competing MCUs. This is going to be critical for edge computing going forward, to which end NXP is working very closely with foundry partner Samsung.
FD-SOI is not just helpful for the logic part of these chips – memory technologies also share in the benefits. They get much higher performance with on-chip flash. Leakage is cut by a factor of ten with biasing techniques, and the enhancements mean that memory can operate at very low voltages.
NXP is increasingly sophisticated with how they use body biasing, applying high-granularity techniques to independent domains in different parts of the chips. Getting sub-0.6 Vmin delivers value at multiple levels: on battery life, on total system cost, and on system enablement. Invest in body biasing if you want to get leadership results, advised Martino.
Edge computing – including machine learning and neural networks for things like image classification – is a big target, he continued. At the last CES they did a proof-of-concept “foodnet” where two appliances talked to each other without having to go to the cloud. In that case it was an i.MX8 in a fridge and an i.MXRT in a microwave, but he explained that the same concept can be applied to a car for driver awareness, where you don’t want to take the extra time for or don’t have a connection to the cloud.
iMX and FD-SOI enable scalable solutions, he concluded.
What’s a metal-bending company doing talking about electrons? asked Audi Project Manager Dr. Andre Blum. And why SOI? Well, for Audi, he said, SOI stands for Solutions, Opportunities and Innovation.
Audi is working on the various levels of autonomous driving, and they want it to be without design limitations. That means being able to hide sensors wherever they’re needed. They’ll create a cocoon around the car for the best driver experience. He showed a fun video Audi’s made to illustrate their concept – it’s the Invisible Man video, which you can check out on YouTube.
But those new architectures can’t up the power budget (think heat): rather they need to cut power drastically while increasing performance. And with FD-SOI, they see an opportunity to do just that, he said, while integrating the sensors.
Audi is one of 25 partners in a heavily funded (>100 million Euros) brand new EU Horizon 2020 program called Ocean12 (lead by Soitec). The launch was only May 1st 2018 (so as of today it doesn’t even have a website yet), and it will run for about 4 years. It is described by ECSEL (a public-private entity that puts together the big EU research projects) as an “opportunity to carry European autonomous driving further with FDSOI technology up to 12nm node”. One to watch!
For Airbus, it’s all about increased connectivity and communications that are trusted and secure, said company expert Olivier Notebaert. Since their chip runs are low, NRE – non-recurring engineering costs – are very important; and they need flexible systems.
SOI has a long history in aerospace – in fact that’s originally where it got its start, since it can handle radiation and is immune to latch-up. Notebaert says that even for Airbus, IoT is their future. The developments they pioneer will be part of it.
Airbus is a partner in the EU Horizon 2020 DAHLIA project – which stands for Deep sub-micron microprocessor for spAce rad-Hard appLIcation Asic. The project is, “…developing a Very High Performance microprocessor System on Chip (SoC) based on STMicroelectonics European 28nm FDSOI technology with multi-core ARM processors for real-time applications, eFPGA for flexibility and key European IPs, enabling faster and cost-efficient development of products for multiple space application domains. The performance is expected to be 20 to 40 times the performance of the existing SoC for space.”
According to another recent presentation, DAHLIA is prototyping an FPGA this year that will be in production in 2019.
For Sony GM Kenichi Nakano, FD-SOI has big potential for low-power products. And he should know. Sony has been an FD-SOI pioneer, using it as the basis for GPS chips that are now in a growing number of cool products, especially watches. They’re getting good feedback from the market and see good opportunities across a diversified global customer base, he said. Their CXD5603, for example, is the lowest power GNSS (GPS) chip worldwide. In mass production since 2015, it is now dominating world wearable markets like trackers — such the popular Amazfit line.
Running through their various FD-SOI based GPS offerings, he noted that the GPS is a pretty simple chip. But now customers are asking for more, like for it to work in the water (where a GPS typically doesn’t). So Sony has partnered with triathalon teams and are seeing good results.
With success, of course, comes greater demands: for greater accuracy, for more precise positioning in motion, for increased height accuracy, for even lower power – and Sony is meeting these demands with FD-SOI, in solutions like the new CXD5602. The CXD5602 product configuration covers audio/video/communications: key factors in IoT. A camera version is releasing this summer, as are main and extension boards. An LTE module will be released at the end of 2018.
And now they’re using those FD-SOI chips in audio applications. You’ll find it in the Xperia™ Ear Duo, he said. The MWC press release noted that Xperia Ear Duo “… is driven by Sony’s ultra-low power consuming “CXD5602” chip and a sophisticated multi-sensor platform, the “Daily Assist” feature will recognize time, location and activities to offer relevant information throughout the day – reminding you what time your next meeting is when you reach the office or narrating the latest news headlines.”
Also in that PR, Hiroshi Ito,Deputy Head of Smart Product Business Group at Sony Mobile Communications, said, “Ear Duo is the first wireless headset to deliver a breakthrough Dual Listening experience – the ability to hear music and notifications simultaneously with sounds from the world around you.” The highly anticipated wireless “open-ear” stereo headset started rolling out to select markets in Spring 2018. There’s a great info page with video here.
So that’s what we heard in the morning. My next post (or posts?) will cover the afternoon. That includes Dan Hutcheson’s excellent talk updating his FD-SOI survey, presentations from Samsung, Globalfoundries and Simgui, plus some from very cool start-ups, and the final panel presentation.
China Mobile is the world’s largest* telco. So when Danni Song, one of the company’s high-level project managers presented at the SOI Consortium’s 5th International RF-SOI Workshop in Shanghai, you can bet people listened. With each new slide, a glowing sea of cell phone cameras rose over the heads of the audience in the huge, packed ballroom.
Over the last month, there’s been a lot more coverage of 5G in the press (especially after the recent Mobile World Congress (MWC) – check out Junko Yoshida’s EETimes piece for example). For ASN readers who want to know more about 5G and RF-SOI in China, here’s a reminder that Song’s presentation, and many of the others given by leading companies at the RF-SOI Workshop last fall, are now posted on and freely available the Consortium website Events page. Click here for the listing and links.
The theme of the workshop was IoT, mobile, 5G connectivity, and mmW. As Dr. Xi Wang, Director General of SIMIT/CAS (the Shanghai Institute of Microsystem & Information Technology in the Chinese Academy of Sciences), said in his opening keynote, China is strong in RF-SOI. RF-SOI will be growing at a CAGR of over 15% for the next five years, and China has production, design, wafer manufacturing and good momentum. “We will make a great contribution to the whole IC industry,” he predicted.
Of note, too, Russell Ellwanter, CEO of TowerJazz, gave what turned out to be a very inspirational keynote about Value Creation, and the importance of treating your suppliers with respect. He credits his company’s close relationship with RF-SOI wafer-supplier Soitec for TJ’s claim to the world’s best linearity. Five of their seven fabs do RF-SOI. LNA (low-noise amplifers) are a big market driver, and with RF-SOI they can integrate the LNA with the switch.
Here are some more highlights from the day – but by all means check out the presentations for details. (You can click on the illustrations to see them in full screen.)
In her presentation, Embrace a Brand New Cooperation in 5G Era, Song asked where RF-SOI could help in her wish list. Could it increase integration and decrease cost and power consumption? Can it help improve NB-IoT device performance? The supply chain needs to come back around into a circle, so that the telcos are connected to and get insights from the wafer substrate providers, she said.
China Mobile has a 5G Innovation Center, and has established test labs in 8 cities. And the government has announced a 5G launch in 2020, with pre-commercial trials now going into 20 cities. So she was at the RF-SOI Workshop as much to listen and learn as to share China Mobile’s vision.
The presentation by Kidetoshi Kawasaki, GM of Sony Semiconductor Solutions, focused on antenna tuning, which he said is one of the fastest growing things in cell phones. Antenna Tuning Progress & SOI Single Chip Integration for 4G/5G UE (note that UE = user equipment) looks at antenna aggregation, and why it is important for carrier aggregation (CA) and MIMO. Sony has developed an SOI-based next-gen process for 5G integrating passive components. That’s why RF-SOI is important and will be continued to be used in the mobile market, he said.
GF has developed demo vehicles to help customers, said Sr. Director of the RF Business Unit, Peter Rabbeni. (Over the years they’ve shipped over 32 billion RF-SOI devices, btw.) In his presentation, RF-SOI: Delivering Performance & Integration for the Next Generation of Mobile,he noted that RF is becoming more complex than digital. As a result there is a need to integrate to help reduce cost: this is a direct correlation to the standards that are driving complexity. At the same time, performance requirements are increasing, so the challenge is driving increased performance at the same or lower cost than previous generations of products.
To meet 4G/LTE and 5G’s evolving performance demands, GF has recently introduced two new RF-SOI platforms, which he detailed in the presentation. 8SW enables increased integration of front-end modules (FEMs), while 45RFSOI is for mmWave FEMs. (In a separate presentation, IDDO-IC CEO Denis Masliah presented a Differential Complementary Millimeter Wave Power Amplifier for 5G using 45RFSOI process, which is currently being fabbed by GF.)
The two leading RF-SOI wafer suppliers, Soitec and partner Simgui, both gave excellent presentations. Though Soitec EVP Bernard Aspar’s presentation Engineered Substrates as Foundation of Innovation in RF is not posted, he made some important points. Up til now, RF-SOI has mainly been about switches and tuners, he said, but there are other opportunities that offer the potential for huge growth. The full supply chain needs to be prepared, he said, and suppliers need to understand each other. Each technology requires the right substrate – and even as we move into sub-6GHz 5G, there is still work to be done in 4G. In fact Soitec is now offering services to help customers better understand new substrate options.
Soitec’s partner in China, Simgui, now uses Soitec’s Smart CutTM technology for RF-SOI wafer production. Together the two are now producing over a million 200mm RF-SOI wafers/year, said Simgui Sr. Director, Kerui Wang. His presentation, RF-SOI – a Secured Substrate Supply Chain, looked at their strategic partnership with Soitec, wherein they use the same tools and processes to deliver the same products meeting the same specs.
Two leading fabless companies – RDA Microelectronics (which was acquired by Spreadtrum) and SmarterMicro also presented their RF-SOI activities. Although their ppts are not posted, here are a few highlights.
Longtime ASN readers will recall that RDA has been shipping high-volume, RF-SOI based chips to Samsung and others for over five years. In the presentation, RF-SOI in Current and Future RFFE Solutions, Engineering AVP Joseph Jia said that over last two years alone they’ve released almost 50 RFFE (front end) chips on RF-SOI. They see RF-SOI as the right match for switches, tuners and NB-IoT because of the low-voltage and tunability advantages.
SmarterMicro’s CTO, Peter Li, sees RF-SOI as a cornerstone of 5G. In his presentation, Reconfigurable RFFE in 5G, he said the goal is smart systems on fewer dies to decrease size and cost.
Jeff Zhu, assistant director at SMIC, presented SMIC, 0.13um RF-SOI Platform Updates. Mainland China’s largest foundry has recently moved its RF-SOI process from 180 to 130um, and he walked us through some chip designs.
Throughout the day, presenters noted that RF is a great opportunity for China to take a leadership position. As one panelist at the end of the day noted, RF depends more on expertise and talent than digital, which depends more on manpower.
Just before the Shanghai events, there was a 2-day event sponsored by the City of Nanjing, co-organized by SOI Industry Consortium and the City of Nanjing. Over 200 participants attended the workshop and tutorials on SOI applications, SoC development and manufacturing, EDA & IP ecosystem, as well as a design tutorial for More than Moore SOI ecosystem. Almost all of those presentations are now posted on the Consortium – click here to get them.
Some of the participants in the SOI Consortium’s delegation also had the opportunity to visit the enormous Nanjing Sofware Park. Nanjing, we learned, is often considered China’s “RF capital”. The list of the world’s major RF players working in partnership there is certainly an international who’s who.
So, lots of good RF-SOI/5G info on the SOI Consortium website – check it out!
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Day 2 of the recent SOI Workshop in Tokyo was dedicated to the “Convergence of IoT, Automotive through Connectivity”. Many of the presentations are now posted and freely available – click here to see the full list.
It was a really full day, so the recap in this post covers about half of the Day 2 presentations. My next post will cover the rest of them. (In case you missed it, Day 1 was covered in my previous post – you can read it here.)
Another Sony GPS Win!
The day kicked off with a talk by Sony GM Kenichi Nakano, entitled Sony Semiconductor Low-Power IoT Solution. He reminded the audience that Sony started looking at FD-SOI in 2013, and announced at ISSCC last year (the paper’s available from the IEEE – click here). Power, he said, is everything.
And that low-power GPS in Casio’s latest Pro Trek Smart watch, the WSD-F20? It’s based on Sony’s new CXD5602 – and that’s on FD-SOI, to which they give largely give credit for the >75% reduction in power from the previous generation.
Samsung: Surf’s Up!
FD-SOI is mature, and they’re ready to surf it, said Principle Designer at Samsung Foundry Marketing, Yongjoo Jeon. But, he added, they’ll continue to evolve it.
Covering a wide range of applications, he sees FD-SOI as a key in the 4th industrial revolution. In terms of power/performance, the “…excellent short channel effect enables better performance and lower power than bulk technology.” And, “Body bias enhances further performance [FBB – forward body bias] and power reduction [RBB – reverse body bias].”
That provides some unique benefits, he pointed out.
in automotive, it’s safety: the physical dielectric isolation is almost free from SER (soft error rate)
for analog/RF, the long channel gain is more significant with excellent noise immunity
for every application, lower doping enhances variation immunity
Samsung reached high yield (defect density D0<0.2) very quickly, and ramped rapidly to mass production (which is where they are with NXP as of Q1/17). This, he said, shows the maturity of their 28FDS FD-SOI technology.
Then he turned to design. Samsung (which does btw, offer Design Services) has an IP portfolio that is wide and deep, with a strong, well-established reference flow, supported by both Cadence and Synopsys.
In terms of RF, 28FDS has better fT than 28nm bulk. The physical isolation of the SOI structures enables a “no guard ring” approach, and specific RF offerings include LDMOS for PAs (power amplifiers). Samsung is supporting a new mm-Wave Pcell, which will be added in the V1.1 PDK.
Samsung is also adding eMRAM (embedded magnetoresistive RAM – it’s already yielding at 60%), as they see 28nm is probably the last node for eflash. “We’re very proud of these technologies,” he said.
Samsung’s next generation of FD-SOI will be 18nm, which provides a 20% increase in performance, a 40% decrease in power, and a 30% reduction in logic area.
Cadence EDA & IP Update
FD-SOI enablement usually means PDKs and tech files, noted Jonathon Smith, Director of Strategic Alliances at Cadence. But for deep benefits, you need to work with the foundries on characterizing libraries, and that’s just what Cadence is doing with both Samsung and GlobalFoundries, he said.
He gave a very frank and interesting talk entitled Enabling an Interconnected Digital World: Cadence EDA & IP Update. IoT, he noted, will include a lot of mixed-signal and complex packaging. Customers need modular reference flows, and they want flexibility and multiple foundry nodes. For FD-SOI, Cadence has been working on PDK enablement, tool readiness and design tools for several years. There is one database for both digital and analog.
For Samsung’s 28FDS, everything from logic synthesis to sign-off and analog tools are certified. In fact Cadence recently announced its custom/analog tools and full-flow digital and signoff tools have achieved Samsung certification for the PDK and foundation library (see the press release here).
For GlobalFoundries 22FDX, Cadence is certified across the entire design flow, and the reference flows are downloadable.
In terms of IP, he acknowledged that what Cadence has is not very extensive, so they are working with both partners and competitors. However, he did point out that their Tensilica IP for automotive is gaining traction: it is used in the Dreamchip ADAS chip fabbed on GF’s 22FDX, for example.
Wait, There’s More!
Day 2 in Tokyo was really packed with excellent presentations – too much for just one post. See Part 2 of my Day 2 coverage for highlights from Leti, GlobalFoundries, Soitec, MIPS/Imagination and more.
Looking for insight into the state of SOI and FD-SOI in Japan? Want to find out who’s doing IP and design support? Wondering about the major drivers? If you’re in the region, you can find out – and network with the top players in the ecosystem – at the 3rd Annual SOI Tokyo Workshop. The SOI Consortium has put together a great line-up of speakers.
This year it will take place over the course of two days, May 31st and June 1st . Click here for registration information on the SOI Consortium website. (While there is no charge for the event, please register in advance to guarantee your place.) You’ll find the full program here. A brief summary follows.
The first day – Wednesday, May 31st – is an afternoon session hosted by Silvaco, with presentations from some of the key players in the FD-SOI Ecosystem. Speakers include top executives from GlobalFoundries and IP/design leaders Synopsys, Silvaco, Invecas and Attopsemi, as well as the SOI Consortium.
It will take place on the 25th floor of the Yokohama Landmark Tower. The reception at the end of the day will give participants an extended opportunity to network with the speakers and other attendees.
The second day of the workshop – Thursday, June 1st – will focus on Convergence of IoT, Automotive Through Connectivity. This full-day workshop, with talks by top executives in the industry, will be held at Tokyo University’s Takeda Hall.
It kicks off with talks on ultra-low power applications from Sony IoT and Samsung. Next up, speakers from Imagination/MIPS, IHSMarkit and Leti address automotive technologies. After lunch, the first group of speakers from GlobalFoundries, Cadence, Nokia and ST tackle IoT, Connectivity and Infrastructure. The day wraps up with talks by some of the key supply chain providers: Applied Materials, Soitec and Screen.
Coffee breaks and lunch will give attendees and speakers time for further discussion.
This is a great opportunity – don’t miss it!
Sony’s 28nm FD-SOI GPS rolling out in the Xiaomi Amazfit smartwatch is “…a big win for Sony” and “…an even bigger win for FD-SOI’s promoters,” said Junko Yoshida of EETimes (see Sony-Inside Huami Watch: Is It Time for FD-SOI?). Then she adds:“Huami’s watch decidedly demonstrates the technology’s claim to ultra-low power consumption.”
Xiaomi is a subsidiary of Huami, which lays claim to being the second largest manufacturer of wearables in the world. So it really is a big win. What’s more, the Amazfit, says Xiaomi, is “…the world’s first smartwatch with a 28 nm GPS sensor”.
Sony has been releasing evolving details of the chip at various conferences over the last few years (including SOI Consortium forums). To get their ISSCC paper, 26.5 A 0.7V 1.5-to-2.3mW GNSS receiver with 2.5-to-3.8dB NF in 28nm FD-SOI (February 2016) from IEEE Xplore – click here.
(Image courtesy xiaomi-mi.com)
The #1 take-away message from the recent FD-SOI Symposium in San Jose is that “FD-SOI is the smart path to success”. With presentations echoing that theme by virtually all the major players – including (finally!) ARM – to a packed house, it really was an epic day for the FD-SOI ecosystem. The presentations are now starting to be available on the SOI Consortium website – click here to see them (they’re not all there as of today, though, so keep checking back).
Since there’s so much to cover, we’ll break this into two parts. This is Part 1, focusing on presentations related to some of the exciting products that are hitting the market using 28nm FD-SOI. Part 2 will focus on the terrific presentations related to 22nm FD-SOI. In future posts we’ll get into the details of many of the presentations. But for now, we’ll just hit the highlights.
So back briefly to FD-SOI being smart. (A nice echo to the Soitec FD-SOI wafer manufacturing technology – SmartCutTM – that make it all possible right?) It started with the CEO of Sigma Designs (watch for their first IoT products on FD-SOI coming out soon) quipping, “FD-SOI is the poor man’s FinFET.” To which GlobalFoundries’ VP Kengeri riffed that really, “FD-SOI is the smart man’s FinFET”. And NXP VP Ron Martino, summed it up saying, “FD-SOI is the smart man’s path to success”. Yes!
Samsung now has a strong 28nm FD-SOI tape-out pipeline for 2016, and interest is rising fast, said Kelvin Low, the company’s Sr. Director of Foundry Marketing. His presentation title said it all: “28FDS – Industry’s First Mass-Produced FDSOI Technology for IoT Era, with Single Platform Benefits.” They’ve already done 12 tape-outs, are working on 10 more now for various applications: application processor, networking, STB, game, connectivity,…., and see more coming up fast and for more applications such as MCU, programmable logic, IoT and broader automotive. It is a mature technology, he emphasized, and not a niche technology. The ecosystem is growing, and there’s lots more IP ready. 28nm will be a long-lived node. Here’s the slide that summed up the current production status:
As you see, the production PDK with the RF add-on will be available this summer. Also, don’t miss the presentations by Synopsys (get it here), which has repackaged the key IP from ST for Samsung customers, Leti on back-bias (get it here), Ciena (they were the Nortel’s optical networking group) and ST (it’s chalk-full of great data on FD-SOI for RF and analog).
If you read Ṙon’s terrific posts here on ASN recently, you already know a lot about where he’s coming from. If you missed them, they are absolute must-reads: here’s Part 1 and here’s Part 2. Really – read them as soon as you’re done reading this.
As he noted in his ASN pieces, NXP’s got two important new applications processor lines coming out on 28nm FD-SOI. The latest i.MX 7 series combines ultra-low power (where they’re dynamically leveraging the full range of reverse back biasing – something you can do only with FD-SOI on thin BOX) and performance-on-demand architecture (boosted when and where it’s needed with forward back-biasing). It’s the first general purpose microprocessor family in the industry’s to incorporate both the ARM® Cortex®-A7 and the ARM Cortex-M4 cores (the series includes single and dual A7 core options). The i.MX 8 series targets highly-advanced driver information systems and other multimedia intensive embedded applications. It leverages ARM’s V8-A 64-bit architecture in a 10+ core complex that includes blocks of Cortex-A72s and Cortex-A53s.
In his San Jose presentation, Ron said that FD-SOI is all about smart architecture, integration and differentiating techniques for power efficiency and performance. And the markets for NXP’s i.MX applications processors are all about diversification, in which a significant set of building blocks will be on-chip. The IoT concept requires integration of diverse components, he said, meaning that a different set of attributes will now be leading to success. “28nm FD-SOI offers advantages that allows scaling from small power efficient processors to high performance safety critical processor,” he noted – a key part of the NXP strategy. Why not FinFET? Among other things, it would bump up the cost by 50%. Here are other parts of the comparison he showed:
For NXP, FD-SOI provides the ideal path, leading to extensions of microcontrollers with advanced memory. FD-SOI improves SER* by up to 100x, so it’s an especially good choice when it comes to automotive security. Back-biasing – another big plus – he calls it “critical and compelling”. The icing on the cake? “There’s so much we can do with analog and memory,” he said. “Our engineers are so excited!”
You know how using mapping apps on your smartphone kills your battery? Well now there’s hope. Sony’s getting some super impressive results with their new GPS using 28nm FD-SOI technology. These GPS are operated at 0.6V, and cut power to 10x (!) less than what it was in the previous generation (which was already boasting the industry’s lowest power consumption when it was announced back in 2013).
In San Jose, Sony Senior Manager Kenichi Nakano presented, “Low Power GPS design with RF circuit by the FDSOI 28nm”, proclaiming with a smile, “I love FD-SOI, too!” All the tests are good and the chip is production ready, he said. In fact, they’ve been shipping samples since March.
As of this writing, his presentation is not yet posted. But til it is, if you’re interested in the background of this chip, you can check out the presentation he gave in Tokyo in 2015 here.
SERDES (Serializer/Deserializer) IP is central to many modern SOC designs, providing a high-speed interface for a broad range of applications from storage to display. It’s also used in high-speed data communications, where it’s had a bad rep for pulling a huge amount of power in data centers. But Analog Bits has been revolutionizing SERDES IP by drastically cutting the power. Now, with a port to 28nm FD-SOI, they’re claiming the industry’s lowest power.
In his presentation, “A Case Study of Half Power SERDES in FDSOI”, EVP Mahesh Tirupattur described FD-SOI as a new canvas for chip design engineers. The company designs parts for multiple markets and multiple protocols. When they got a request to port from bulk to 28nm FD-SOI, they did it in record time of just a few months, getting power down to 1/3 with no extra mask steps. Plus, they found designing in FD-SOI to be cheaper and easier than FinFET, which of course implies a faster time to market. “The fabs were very helpful,” he said. “I’m pleased and honored to be part of this ecosystem.”
Listening to a presentation by Stanford professor Boris Murmann gets you a stunning 30,000 foot view of the industry through an amazing analog lens. He’s lead numerous explorations into the far reaches of analog and RF in FD-SOI, and concludes that the technology offers significant benefits toward addressing the needs of: ultra low-power “fog” computing for IoT (it’s the next big thing – see a good Forbes article on it here); densely integrated, low-power analog interfaces; universal radios; and ultra high-speed ADC. Get his symposium presentation, “Mixed-Signal Design Innovations in FD-SOI Technology” here.
So, it was a great day in San Jose for 28nm FD-SOI. Next in part 2, we’ll look at why it was also an epic day for 22nm FD-SOI. Be sure to keep checking back at the SOI Consortium website, as more presentations will become available in the days to come.
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*SER = Soft Error Rates – soft errors occur when alpha or neutron particles hit memory cells and change their state, giving an incorrect read. These particles can either come from cosmic rays, or when radioactive atoms are released into the chips as materials decay.
The SOI Consortium has lined up an excellent, comprehensive FD-SOI Symposium on April 13th in San Jose. They’ll be highlighting the tremendous progress of the FD-SOI ecosystem. Headliners include Cisco, Sony, NXP, SigmaDesigns, ARM, Ciena plus the big FD-SOI foundries, EDA companies, design partners, chipmakers and analysts. There is a special session dedicated to RF and analog design innovation on FD-SOI with STMicroelectronics, Stanford and others. In short, we’re going to get a chance to see the FD-SOI ecosystem in action.
To attend, all you have to do is register in advance – click here to go to the registration page. It’s free and open to everyone who registers.
08:00AM – 09:00AM – Registration
08:55AM – 09:00AM – Welcome by Carlos Mazure, SOI Consortium
09:00AM – 09:30AM – Aglaia Kong, Cisco Systems, CTO for Internet of Everything
09:30AM – 10:00AM – Thinh Tran, Sigma Designs, CEO
10:00AM – 10:30AM – Ron Martino, NXP, VP, Application Processors & Advanced Technology Adoption
10:30AM – 10:50AM – Coffee Break
10:50AM – 11:20AM – Subramani Kengeri, GLOBALFOUNDRIES, VP CMOS Business Unit
11:20AM – 11:50AM – Will Abbey, ARM, GM Physical IP
11:50AM – 12:20PM – Kelvin Low, Samsung Semiconductor, Senior Director, Foundry Marketing
12:20PM – 1:40PM Lunch
1:40PM – 2:10PM – Kenichi Nakano, SONY, Sr. Manager, Analog LSI Business Division
2:10PM – 2:40PM – Dan Hutcheson, VLSI Research, CEO
2:40PM – 3:05PM – Mahesh Tirupattur, Analog Bits, EVP
3:05PM – 3:30PM – Mike McAweeney, Synopsys, Sr. Director, IP Division
3:30PM – 4:00PM – Coffee Break
4:00PM – 4:30PM – Naim Ben-Hamida, Ciena, Senior Manager
4:30PM – 4:55PM – Rod Metcalfe, Cadence, Group Director, Product Engineering
4:55PM – 5:20PM – Prof. Boris Murmann, Stanford, on “Mixed-Signal Design Innovations in FD-SOI Technology”
5:20PM – 5:45PM – Frederic Paillardet, STMicroelectronics, Sr. Director, RF R&D
5:45PM – 6:00PM – Ali Erdengiz, CEA-LETI, Silicon Impulse
6:00PM – 6:05PM – Closing remarks by Giorgio Cesana, SOI Consortium
Please note that if you’ve already registered last month when the first announcement went out, the location has changed. The SOI Consortium FD-SOI Symposium will be held on Wednesday, 13 April 2016, from 8am to 6:30pm at the:
Doubletree Hotel San Jose
2050 Gateway Place
San Jose, California 95110, USA
If you can’t make it, not to worry – ASN will be there taking notes for a round-up and follow-up articles. Plus we’ll be tweeting and retweeting (follow us on Twitter at @FollowASN and @AdeleHars – look for the hashtag #FDSOI). And of course you’ll want to follow the Twitter feeds of participating companies, and of the SOI Consortium @SOIConsortium.org.
A recent post by Eric Esteve on SemiWiki, entitled Sony Endorses FD-SOI to Attack Wearable & IoT (click here to read it) delves into some of the technical and design details of Sony’s Tokyo presentation on a 1mW 28nm FD-SOI GPS. (The full presentation is available here. Or click here to read the ASN overview of all the Tokyo presentations.) For the design community, IP expert Esteve talks about how Sony dramatically lowered the supply voltage, and looks at active power consumption, leakage, intrinsic gain and noise. He concludes, “FD-SOI penetration in consumer applications has started.”
ARM is working on FD-SOI libraries, and the ecosystem is now there, says David Manners of Electronics Weekly. In two separate pieces, he cited conversations with ARM EVP Pete Hutton. In Microcontrollers Become Major at ARM (click here to read it), Hutton confirmed both the FD-SOI libraries and customers. In Cinderella (click here to read it), Manners looked at all the FD-SOI pieces – the recent Sony GPS presentation, involvement of players such as ARM, Samsung, Verisilicon, Open Silicon, Synopsys and Cadence – and concluded that, “Cinderella is finally going to the ball.”