For the second consecutive year the SOI Consortium will have a stand at the Networking Reception during the Samsung Foundry Forum (SFF). This important Silicon Valley event will be held on May 14, 2019 at the Santa Clara Marriott. We hope you’ll stop by to learn more about the SOI Consortium and the FD-SOI ecosystem.
There’s been a steady stream of news about Samsung’s FD-SOI offerings and support, including their highly successful 28FDS and coming very soon: 18FDS. (If you need to catch up, click here to read more.) As in the previous 3 years, Samsung will be making major announcements on their technology roadmap and application solutions. SFF is a unique opportunity to network with Korean and US based executives from Samsung Foundry as well as customers and ecosystem partners.
SOI Consortium members ARM, Synopsys, Cadence, Analog Bits, VeriSilicon and Xpeedic will also have stands, and NXP will be on the customer panel.
Seats are limited, so go to http://www.samsungfoundryforum.com/2019/ to register now.
Note to our readers: Semiwiki Founder Dan Nenni recently wrote an excellent piece on the importance of the Synopsys investment in automotive IP for GlobalFoundries’ 22FDX (FD-SOI) technology. He graciously has given us permission to reprint it here in ASN.
IP vendors have always had the inside track on the status of new process nodes and what customers are planning for their next designs. This is even more apparent now that systems companies are successfully doing their own chips by leveraging the massive amounts of commercial IP available today. Proving once again that IP really is the foundation of modern semiconductor design.
Automotive is one of those market segments where systems companies are doing their own chips. We see this first hand on SemiWiki as we track automotive related blogs and the domains that read them. To date we have published 354 automotive blogs that have been viewed close to 1.5M times by more than 1k different domains.
The recent press release by Synopsys and GLOBALFOUNDRIES didn’t get the coverage it deserved in my opinion and the coverage it got clearly missed the point. Synopsys, being the #1 EDA and #1 IP provider, has the semiconductor inside track like no other. For Synopsys to make such a big investment in FD-SOI (GF FDX) for automotive grade 1 IP is a huge testament to both the technology and the market segment, absolutely.
I talked to John Koeter, Vice President of Marketing for IP, Services and System Level Solutions. John is a friend and one of the IP experts I trust. 3 years ago Synopsys got into automotive grade IP and racked up 25 different customer engagements just last year. The aftermarket electronics for adding intelligence (autonomous-like capabilities, cameras, lane and collision detection, etc…) to older vehicles is also heating up, especially in China.
I also talked to Mark Granger, Vice President of Automotive Product Line Management at GLOBALFOUNDRIES. Mark has been at GF for two years, prior to that he was with NVIDIA working on autonomous chips with deep learning and artificial intelligence. According to Mark, GF’s automotive experience started with the Singapore fabs acquired from Chartered in 2010. The next generation automotive chips will come from the Dresden FDX fabs which are right next door to the German automakers including my favorite, Porsche.
One thing we talked about is the topology of the automotive silicon inside a car and the difference between central processing and edge chips. Remember, some of these chips will be on glass or mirrors or inside your powertrain. The edge chips are much more sensitive to power and cost so FDX is a great fit.
Mark provided a GF link for more information:
Here is the link to our Automotive resources:
One thing Mark, John, and I agree on is that truly autonomous cars for the masses is still a ways out but we as an industry are working very hard to get there, absolutely.
Here is the press release:
Synopsys and GLOBALFOUNDRIES Collaborate to Develop Industry’s First Automotive Grade 1 IP for 22FDX Process
Synopsys’ Portfolio of DesignWare Foundation, Analog, and Interface IP Accelerate ISO 26262 Qualification for ADAS, Powertrain, 5G, and Radar Automotive SoCs
MOUNTAIN VIEW, Calif., and SANTA CLARA, Calif., Feb. 21, 2019 /PRNewswire/ —
Synopsys, Inc. (Nasdaq: SNPS) and GLOBALFOUNDRIES (GF) today announced a collaboration to develop a portfolio of automotive Grade 1 temperature (-40ºC to +150ºC junction) DesignWare® Foundation, Analog, and Interface IP for the GF 22-nanometer (nm) Fully-Depleted Silicon-On-Insulator (22FDX®) process. By providing IP that is designed for high-temperature operation on 22FDX, Synopsys enables designers to reduce their design effort and accelerate AEC-Q100 qualification of system-on-chips (SoCs) for automotive applications such as eMobility, 5G connectivity, advanced driver assistance systems (ADAS), and infotainment. The Synopsys DesignWare IP implements additional automotive design rules for the GF 22FDX process to meet stringent reliability and operation requirements. This latest collaboration complements Synopsys’ broad portfolio of automotive-grade IP that provides ISO 26262 ASIL B Ready or ASIL D Ready certification, AEC-Q100 testing, and quality management.
“Arbe’s ultra-high-resolution radar is leveraging this cutting-edge technology that enabled us to create a unique radar solution and provide the missing link for autonomous vehicles and safe driver assistance,” said Avi Bauer, vice president of R&D at Arbe. “We need to work with leading companies who can support our technology innovation. GF’s 22FDX technology, with Synopsys automotive-grade DesignWare IP, will help us meet automotive reliability and operation requirements and is critical to our success.”
“GF’s close, collaborative relationships with leading automotive suppliers and ecosystem partners such as Synopsys have enabled advanced process technology solutions for a broad range of driving system applications,” said Mark Ireland, vice president of ecosystem partnerships at GF. “The combination of our 22FDX process with Synopsys’ DesignWare IP enables our mutual customers to speed the development and certification of their automotive SoCs, while meeting their performance, power, and area targets.”
“Synopsys’ extensive investment in developing automotive-qualified IP for advanced processes, such as GF’s 22FDX, helps designers accelerate their SoC-level qualifications for functional safety, reliability, and automotive quality,” said John Koeter, vice president of marketing for IP at Synopsys. “Our close collaboration with GF mitigates risks for designers integrating DesignWare Foundation, Analog, and Interface IP into low-power, high-performance automotive SoCs on the 22FDX process.”
For more information on Synopsys DesignWare IP for automotive Grade 1 temperature operation on GF’s 22FDX process:
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About the Author
Daniel Nenni has worked in Silicon Valley for over 35 years with computer manufacturers, electronic design automation software, and semiconductor intellectual property companies. He is the founder of SemiWiki.com (an open forum for semiconductor professionals) and the co-author and publisher of “Fabless: The Transformation of the Semiconductor Industry”, “Mobile Unleashed: The Origin and Evolution of ARM Processors in our Devices” and “Prototypical: The Emergence of Prototyping for SoC Design”. He is an internationally recognized business development professional for companies involved with the fabless semiconductor ecosystem.
Suddenly they’re everywhere: opportunities to learn more about FD-SOI and RF-SOI. Over the next couple of months you can find them in China, Europe and Silicon Valley. Some are organized by the SOI Consortium, others by foundries and partners.
Here’s a quick listing with links for more info on how to register for upcoming China events.
Nanjing, China. SOI Workshop & Tutorial, 21-22 September 2017.
Organized by the Nanjiing city government and the SOI Consortium. The first day is packed with top presenters, including NXP, ST, Samsung, GlobalFoundries, Cadence, Synopsys, as well as design and IP partners. The second day is a tutorial covering FD and RF-SOI, as well as imagers and photonics. Sessions will be given by Synopsys, Silvaco, Incize, ST, Soitec, and the SOI Consortium.
Shanghai, China. FD-SOI Tutorial. 25 September 2017.
Organized by VeriSilicon and the SOI Consortium. Tutorial covers: tech overview; analog/RF/mixed-signal; neuromorphic and IoT processors; EDA & design process flow; eNVM; and using forward & reverse body bias. Session leaders are from SOI Consortium, GlobalFoundries, ST, Soitec, UCBerkley, Evaderis and Greenwaves.
Shanghai, China. FD-SOI Forum. 26 September 2017.
Organized by VeriSilicon, Simgui, SIMIT and the SOI Consortium. The focus is on Ultra Low Power computing, RF, EDA/IP ecosystem growth and accelerating adoption. Presentations by Dr. Xi Wang of China’s SIMIT/CAS, GF’s CEO Dr. Sanjay Jha, Samsung’s EVP & GM Dr. ES Jung, as well as from Ron Martino, VP & GM from NXP; Paul Boudre, CEO of Soitec; IBS, NSIG, GF, UC Berkeley, VeriSilicon, Cadence and Synopsys. There’s also a very impressive line-up for a final panel discussion.
Shanghai, China. International RF-SOI Workshop. 27 September 2017.
Organized by Simgui, Sitri, SIMIT, VeriSilicon and the SOI Consortium. Now in its 5th year, this conference has grown very quickly: last year it was in a ballrooom with standing room only (note that RF-SOI chips are now found in pretty much every smart phone on the planet). The focus this year is on IoT, mobile, 5G connectivity, and mmW. Keynotes are from TowerJazz, Sony and China Mobile. Presentations from RDA, SMIC, Simgui, Will-Micro, GF, Soitec, Silvaco and Screen.
BTW, for events organized by the SOI Consortium, many of the presentations are available on the website (from Tokyo this summer, for example, and Silicon Valley last spring – and going on back through 2015). Scroll down through Events to Past Events to find them.
Before summer’s no more than a twinkle in our eyes, let’s take a moment to catch up on a key event where FD-SOI took center stage: Leti Innovation Days. French research powerhouse Leti was celebrating 50 years of innovation, so it was a real gala event.
FD-SOI and other SOI technologies were seen and heard throughout the presentations and in the exhibition spaces. But there were a couple of things that were especially interesting that I’ll cover here in ASN. In particular, a panel discussion with GF, Synopsys and Qualcomm; and the big announcement from Leti and Fraunhofer supporting continued FD-SOI development.
(There were also some great info about body biasing in FD-SOI, but we’ll save that for a future post.)
The Panel & More
A session on Micro-nano Pathfinding and the Digital Revolution featured a fascinating panel discussion on Future Applications and New Technologies. As Rajesh Pankaj from Qualcomm, Alain Mutricy from GF and Antun Domic from Synopsys discussed the prospects, FD-SOI quickly took center stage.
Here are some FD-SOI observations from GF’s Alain Mutricy:
It’s planar, so it’s not hard to design in.
It’s the only technology that can get down to 0.4V, and it has the lowest leakage/cell. That will be key for all mainstream applications (except high-end servers) for at least a decade or two.
12 FDX with forward body bias (FBB) will get 7nm FinFET performance.
They’re looking forward to broad FD-SOI adoption. It will enable the next wave of technology and mobile devices.
Synopsys’ Antun Domic noted that:
Currently, 50% of silicon area comes from just 3 or 4% of designs. FD-SOI makes design simpler, so the EDA companies are looking for it to open the door to more designs.
From a design perspective, three thresholds was standard, but that’s not enough. Place and route could stretch to 10 or 15 corners. FD-SOI simplifies tool flow and cuts mask costs. It’s less complicated than you think.
That tech session, btw, began with an excellent testimonial by Leti partner, Soitec. (Remember: the technological innovation that enabled modern SOI wafers came out of Leti and was industrialized by Soitec.) Check out the snapshot below to get an idea of all the areas that SOI-based technologies address.
Leti, Fraunhofer & FD-SOI
The big piece of news to come out of Leti Days is that Leti is teaming up with Fraunhofer to “…strengthen microelectronics innovation in France and Germany” (read the press release here). The agreement was signed by Leti CEO Marie Semeria and Fraunhofer Group for Microelectronics Chairman Hubert Lakner at an official ceremony. A lively the press conference followed. Prof. Lakner emphasized that they are working on a common European roadmap, with a clear plan for collaboration on FD-SOI. Europe, he said, is a good idea, and working together, France and Germany can do a lot for industry. For FD-SOI, Leti is focused on the front-end, and Fraunhofer is working on the back-end.
Working together, they can elevate pillars like FD-SOI from the country level to the European level, noted Dr. Semeria. And that puts them in a more elevated position for EC funding initiatives such as an upcoming IPCEI – which stands for Important Project of Common European Interest.
Initially, however, the focus will be on extending CMOS and More-than-Moore technologies to enable next-generation components for applications in IoT, augmented reality, automotive, health, aeronautics and other sectors, as well as systems to support French and German industries. A second phase extending to other partners and countries is possible. We’ll keep you posted.
In closing, I’m sure you’ll all join me in extending hearty congratulations to Leti on their 50th anniversary. And here’s to their next 50 years of innovation – can you imagine what that might bring? It rather boggles the mind, doesn’t it?
Synopsys’ custom design platform has been certified by Samsung Electronics for its 28FDS (FD-SOI) process technology. The certified Synopsys custom design platform includes HSPICE® golden-accuracy circuit simulation, Custom Compiler™ visually-assisted layout automation, StarRC™ gold-standard parasitic extraction and IC Validator scalable physical signoff. The Synopsys custom design platform provides improved custom and mixed-signal design productivity for Samsung 28FDS users designing for various low power required applications such as IoT, connectivity, mobile computing and automotive. (Read the full press release here.)
“Samsung Foundry’s certification of Synopsys’ custom design platform is important to our mutual customers developing complex designs,” said Bijan Kiani, vice president of product marketing at Synopsys. “Through close collaboration, we have delivered a certified custom tool suite and accompanying iPDK to enable our mutual customers to improve their custom layout and circuit simulation productivity.”
Custom Compiler’s user-guided symbolic editing technology accelerates 28FDS device placement. It includes interactive custom routing technology that can quickly create DRC-correct routing, thus reducing late-stage physical signoff iterations. The combination of placement and routing assistants in the Custom Compiler solution cuts 28FDS layout effort by up to 30 percent. Custom Compiler support for these advanced features is provided through a jointly developed 28FDS PDK in the industry-standard interoperable (iPDK) format.
“Samsung Foundry’s 28FDS delivers lower design cost, lower total power and better analog performance, making it suitable especially for low power driven applications such as IoT and connectivity,” said Jaehong Park, senior vice president of the Foundry Design Team at Samsung Electronics. “We worked with Synopsys to certify Synopsys’ custom design platform for our 28FDS process technology to enable our customers to accelerate their custom design development.”
Looking for insight into the state of SOI and FD-SOI in Japan? Want to find out who’s doing IP and design support? Wondering about the major drivers? If you’re in the region, you can find out – and network with the top players in the ecosystem – at the 3rd Annual SOI Tokyo Workshop. The SOI Consortium has put together a great line-up of speakers.
This year it will take place over the course of two days, May 31st and June 1st . Click here for registration information on the SOI Consortium website. (While there is no charge for the event, please register in advance to guarantee your place.) You’ll find the full program here. A brief summary follows.
The first day – Wednesday, May 31st – is an afternoon session hosted by Silvaco, with presentations from some of the key players in the FD-SOI Ecosystem. Speakers include top executives from GlobalFoundries and IP/design leaders Synopsys, Silvaco, Invecas and Attopsemi, as well as the SOI Consortium.
It will take place on the 25th floor of the Yokohama Landmark Tower. The reception at the end of the day will give participants an extended opportunity to network with the speakers and other attendees.
The second day of the workshop – Thursday, June 1st – will focus on Convergence of IoT, Automotive Through Connectivity. This full-day workshop, with talks by top executives in the industry, will be held at Tokyo University’s Takeda Hall.
It kicks off with talks on ultra-low power applications from Sony IoT and Samsung. Next up, speakers from Imagination/MIPS, IHSMarkit and Leti address automotive technologies. After lunch, the first group of speakers from GlobalFoundries, Cadence, Nokia and ST tackle IoT, Connectivity and Infrastructure. The day wraps up with talks by some of the key supply chain providers: Applied Materials, Soitec and Screen.
Coffee breaks and lunch will give attendees and speakers time for further discussion.
This is a great opportunity – don’t miss it!
ARM is stepping up its effort to support the FD-SOI ecosystem. “Yes, we’re back,” confirmed Ron Moore, VP of ARM’s physical design group. This and much more good news came out of the recent FD-SOI Symposium organized in Silicon Valley by the SOI Consortium.
The full-day Symposium played to a packed room, and was followed the next day by a full-day design tutorial. Though it was a Silicon Valley event, people flew in from all over the world to be there. (BTW, these symposia and tutorials will also be offered in Japan in June, and Shanghai in the fall). I’ll cover the Silicon Valley FD-SOI design tutorial (which was excellent, btw) in a separate post.
Most of the presentations are now posted on the SOI Consortium website. Here in this ASN post, I’ll touch on some of the highlights of the day. Then in upcoming posts I’ll cover the presentations from Samsung and GlobalFoundries.
If you’re designing in FD-SOI, we’ll help: that was the key message from ARM’s Ron Moore during the panel discussion at the end of the day. Earlier that morning, he’d given an excellent presentation entitled Low-Power IP: Essential Ingredients for IoT Opportunities.
CAGR for most IoT units is roughly 50%, he said, counting home (1.6B units by 2020), city (1.8B), industrial (0.6B) and automotive (1.1B). Compare that to the 2.8B smart phones – which he sees as a remote control and display device. The key differentiator for IoT is that 90% of the time the chip is idle, so you really don’t want leakage.
FD-SOI, he said, gives you a silicon platform that’s highly controllable, enables ultra-low power devices, and is really good with RF. ARM’s worked with Samsung’s 28FDS FD-SOI offering comparing libraries on bulk and FDSOI, for example, and came up with some impressive figures (see the picture below).
The foundry partners and wafer providers are in place. So now ARM is asking about which subsystems are needed to fuel FD-SOI adoption. Ron recognizes that the ARM IP portal doesn’t yet have anything posted for FD-SOI, but they know they need to do it. He called on the SOI Consortium to help with IoT reference designs and silicon proof points.
In the Q&A, audience member John Chen (VP of Technology and Foundry Management at NVIDIA) asked about FD-SOI and low-cost manufacturing of IoT chips. Moore replied that we should be integrating functionality and charging a premium for IoT chips – this is not about your 25-cent chip, he quipped.
Geoff Lees, SVP & GM of NXP’s Microcontroller business gave a terrific talk on their new i.MX 7 and 8 chips on 28nm FD-SOI. (And Rick Merritt gave it great coverage in EETimes – see NXP Shows First FD-SOI Chips.)
NXP’s been sampling the i.MX 7 ULP to customers over the last six months, the i.MX 8QM is ramping, and the i.MX 8QXP, 8Q and 8DX are enroute. Each of these chips is optimized for specific applications using biasing. A majority of the design of each chip is hard re-use, and the subsystems can be lifted and dropped right into the next chip in the series. Power consumption and leakage are a tiny fraction of what they’d had been in previous generations. Ultra low power (aka ULP) is heading to new levels, he says.
With FD-SOI, it’s easy to optimize at multiple points: in the chip design phase, in the production phase and in the use phase. They can meet a wide range of use cases, precisely targeting for power usage. FD-SOI makes it a win-win: it’s a very cost effective way to work for NXP, plus their customers today need that broader range of functionality from each chip.
Geoff tipped his hat to contributions made here by Professor Boris Murmann of Stanford, who’s driving mixed signal and RF into new areas, enabling high-performance analog and RF integration. (Folks attending the FD-SOI tutorial the next day had the good fortune to learn directly from Professor Murmann.)
Finally, he cited something recently pointed out by Soitec (they’re the SOI wafer folks) Chief Scientist Bich-Yen Nguyen: if half your chip is analog and/or RF, she’s observed, the future is very bright indeed for FD-SOI.
Briefly, here are some more highlights.
Synopsys: John Koeter, VP of the Marketing Solutions group showed slides of what they’ve done in terms of IP for Samsung and GlobalFoundries’ FD-SOI offerings. But there’s a lot they’ve done with partners he couldn’t show because it’s not public. In terms of tools and flows, it’s all straightforward.
Dreamchip: Designing their new chip in 22nm FD-SOI was 2.5x less expensive than designing it in FinFET would have been, said COO Jens Benndoorf in his presentation, New Computer Vision Processor Chip Design for Automotive ADAS CNN Applications in 22nm FDSOI. One application for these chips (which taped out in January) will be “digital mirroring”: replacing sideview mirrors with screens. Why hasn’t this been done before? Because LED flickering really messes with sensor readings – but they’ve mastered that with algorithms. The chip will also be used for 360o top view cameras and pedestrian detection. They’re using Arteris IP for the onchip networking, and implemented forward body bias (FBB). The reference platform they created for licensing has generated lots of interest in the automotive supply chain, he said.
Greenwaves: CEO Loic Lietar talked about the high performance, ultra-low power IoT applications processor they’re porting from bulk to FDSOI with a budget of just three million euros. The RISC-V chip leverages an open source architecture (which he says customers love) and targets smart city, smart factory, security and safety applications. As such, it needs to wake up very fast using just microwatts of power – a perfect match for body biasing in FD-SOI.
Leti: In her talk about roadmaps, CEO Marie-Noelle Semeria said the main two drivers they’re seeing in the move to FD-SOI are #1: low power (a customer making chips for hearing aids can cut power by 8x using body biasing, for example) and #2: RF (with Ft and Fmax performance that “…will be hard for FinFET to achieve”). Leti knows how to pull in all kinds of boosters, and is finding that RF performance is still excellent at the 10/7nm node. They’ve developed a low-power IoT platform with IP available for licensing. Other recent FD-SOI breakthroughs by Leti include: demonstration of a 5G mmW 60GHz transceiver developed with ST; the first 300mm Qbit, opening the door to quantum computing; a photodiode opening the door to a light-controlled SRAM; and a new 3D memory architecture leveraging their CoolCubeTM that they’re working on with Stanford.
IBS: CEO Handel Jones predicts that there “will be war in the year to come” at the 22nm node, as all the big foundries take aim. FD-SOI is the best technology for RF, ULP and AMS, and there’s a huge market for it. He also said China made the right decision to support FD-SOI, and will come out ahead in 5G.
The day ended with a lively panel discussion (moderated by yours truly) featuring experts from ARM, GF, Invecas, Soitec, Synopsys, Verisilicon and Sankalp. IP availability was a big theme, but generally there was agreement that while some gaps still exist, they’re being filled: lack of IP is no longer an issue. Soitec VP Christophe Maleville confirmed that the wafers for FD-SOI are readily available and that they’re seeing excellent yields.
All in all, it was another really good day for FD-SOI in Silicon Valley.
12nm FD-SOI has now officially joined the GlobalFoundries’ roadmap, targeting intelligent, connected systems and beating 14/16nm FinFET on performance, power consumption (by 50%!) and cost (see press release here). Customer product tape-outs are expected to begin in the first half of 2019. GloFo also announced FDXcelerator™, an ecosystem designed to give 22FDX™ SoC design a boost and reduce time-to-market for its customers (press release here).
The news turned heads worldwide (hundreds of publications immediately picked up the news) – and especially in China. “We are excited about the GlobalFoundries 12FDX offering and the value it can provide to customers in China,” said Dr. Xi Wang, Director General, Academician of Chinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology. “Extending the FD-SOI roadmap will enable customers in markets such as mobile, IoT, and automotive to leverage the power efficiency and performance benefits of the FDX technologies to create competitive products.”
Wayne Dai, CEO of VeriSilicon (headquartered in Shanghai but designing for the world’s biggest names in the chip biz), added, “We look forward to extending our collaboration with GlobalFoundries on their 12FDX offering and providing high-quality, low-power and cost-effective solutions to our customers for the China market. The unique benefits of FD-SOI technologies enable us to differentiate in the automotive, IoT, mobility, and consumer market segments.”
The ultra-thin FD-SOI wafers are where it all starts, and they’re ready to go in high volume, says Paul Boudre, CEO of SOI wafer leader Soitec. “We are very pleased to see a strong momentum and a very solid adoption from fabless customers in 22FDX offering,” he adds. “Now this new 12FDX offering will further expand FD-SOI market adoption. This is an amazing opportunity for our industry just in time to support a big wave of new mobile and connected applications.”
GloFo’s 12FDXTM platform, which builds on the success of its 22FDXTM offering, is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles. Increased integration of intelligent components including wireless (RF) connectivity, non-volatile memory, and power management—all while driving ultra-low power consumption—are key 12FDX selling points that FinFETs can’t touch.
The technology also provides the industry’s widest range of dynamic voltage scaling and unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate in energy efficiency.
“Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said GLOBALFOUNDRIES CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.”
Kudos came in from G. Dan Hutcheson, CEO of VLSI Research, IBS CEO Handel Jones, Linley Group Founder Linley Gwennap, Dasaradha Gude, CEO of IP/design specialists INVECAS, Leti CEO Marie Semeria and NXP VP Ron Martino (they’ve already started on 28nm FD-SOI for their i.MX line – read his superb explanations in ASN here).
Simultaneously to the 12FDX announcement, GloFo announced the FDXcelerator Partner Program. It creates an open framework under which selected Partners can integrate their products or services into a validated, plug and play catalog of design solutions. This level of integration allows customers to create high performance designs while minimizing development costs through access to a broad set of quality offerings, specific to 22FDX technology. The Partner ecosystem positions members and customers to take advantage of the broad adoption and accelerating growth of the FDX market.
Initial partners of the FDXcelerator Partner Program are: Synopsys (EDA), Cadence (EDA), INVECAS (IP and Design Solutions), VeriSilicon (ASIC), CEA Leti (services), Dreamchip (reference solutions) and Encore Semi (services). These companies have already initiated work to deliver advanced 22FDX SoC solutions and services.
Initial FDXcelerator Partners have committed a set of key offerings to the program, including:
Additional FDXcelerator members will be announced in the following months.
If you’re headed to DAC (June 5-9 in Austin,TX) and are interested in learning more about FD-SOI, there will be lots of opportunities. Here’s a quick rundown.
Synopsys (stands 149 & 361) and GlobalFoundries are hosting a dinner on Tuesday evening (7 June) at the Austin Hilton around the theme, What’s Important for IoT—Power, Performance or Integration… or All of the Above? They’ll be talking about how FD-SOI addresses these challenges. Panel members will discuss design techniques to push the envelope on low power, low leakage, burst performance and optimal cost to enable the design of innovative IoT-based products. Attendance is free, but registration is required and seating is limited. Click here to go to the registration site.
Samsung Foundry (stands 607 and 706) and partners will be doing a number of presentations on Samsung’s 28nm FD-SOI offering, 28FDS. They’ll be showcasing 28FDS wafers, offering multiple presentations by Samsung Foundry’s experts, and sharing solutions built on the 28FDS technology by their Foundry Ecosystem partners. As noted in ASN coverage of the recent SOI Consortium event in San Jose (read it here), Samsung is now in commercial production of 28FDS. They have a strong 28nm FD-SOI tape-out pipeline for 2016, and interest is rising fast.
IP Track: Minimizing SOC Power Consumption: A Top Down Design Methodology or Bottoms Up Starting With the Process Selection Problem? Panelists include Carlos Mazure (of the SOI Industry Consortium & Soitec) and Ron Martino (of NXP) Monday, June 6th from 4:00pm – 5:00pm in Ballroom G.
Variation-Aware Design at Advanced and Low-Power Processes. Panelists include Azeez Bhavnagarwala (ARM), Glen Wiedemeier (IBM), John Barth (Invecas) and Jeff Dyck (Solido). Monday, June 6th from 10:30am – 11:30am, Room: 9BC.
Presentation 9.1 Impact of Leakage & biasing on Power in 22FDX Process. By Krishnan Subramanian et al (Invecas) and Sankar Ramachandran – (Apache Design). Monday, June 6th, 3:30pm – 4:00pm, Ballroom G.
Presentation 50.4 Leveraging FDSOI through Body Bias Domain Partitioning and Bias Search. By Johannes M. Kuehn et al (Eberhard Karls Univ. Tubingen & Keio Univ.) Wednesday, June 8th, 1:30pm – 3:00pm, Room: 17AB. This presentation will be given at 2:15. (You can also get the paper from the ACM site here.)
101.12 Parametric Exploration for Energy Management Strategy Choice in 28nm UTBB FDSOI Technology. By Jorge Rodas et al (CEA-Leti Minatec & Univ. Grenoble Alpes) Work-in-Progress (WIP) poster session, Wednesday, June 8th, 6:00pm – 7:00pm, Room: Trinity St. Foyer
Stands & More
Cadence Theater (stand 43 – full schedule here)
Tuesday, June 7th
Wednesday, June 8th
Leti (stand 1818) – a driving force behind all things SOI, stop by to learn more about Silicon Impulse®, their FD-SOI platform for IoT & ultra-low-power (ULP) apps that helps start-ups, SMEs and large companies evaluate, design, prototype & move to volume (more here).
And finally, the opening keynote on Monday morning (at 9:15 in Ballroom A) will be given by NXP’s Lars Reger, CTO of their Automotive Business Unit. The topic is Revolution Ahead – What It Takes to Enable Securely Connected, Self-Driving Cars. When it comes to automotive, NXP is the original SOI pioneer, dating to back to 1999. NXP’s sold billions of SOI-based chips for high-voltage automotive applications – they’re used by virtually every carmaker on the planet (read about the early history here and here).
And now with the Freescale acquisition, NXP is full speed ahead with FD-SOI applications processors. If you missed it, you’ve got to read the recent ASN series by Ron Martino (NXP’s VP for i.MX Applications Processor and Advanced Technology Adoption). He explains why they chose 28nm FD-SOI, and exactly what it does for the i.MX 7 series (32-bit ARM v7-A core, targeting the general embedded, e-reader, medical, wearable and IoT markets) and i.MX 8 series (64-bit ARM v8-A series, targeting automotive applications, especially driver information systems, as well as high-performance general embedded and advanced graphics applications) Click here to read it now. NXP gave a demo of the I.MX 8 at FTF 2016 a few weeks ago – check out the video they posted on Twitter here.
If you go to DAC and you have a Twitter account, be sure to tweet #FDSOI and #53rdDAC – @followASN will be happy to pass it along!
This is part 2 (of 2) of ASN’s coverage of the epic FD-SOI Symposium in San Jose. In part 1 we looked at the exciting developments happening at 28nm (if you missed it, click here to read it now). Here in part 2, we’ll look at 22nm, covering the presentations by GlobalFoundries, ARM, VLSI Research and Sigma Designs. Again, the presentations are now starting to be available on the SOI Consortium website – click here to see them (they’re not all there as of today, though, so keep checking back).
Dan Hutcheson, CEO of VLSI Research, has come around to FD-SOI. His excellent talk, “FD-SOI: Disruptive or Just Another Process” (click here to download it), concluded that FD-SOI is not disruptive – but it’s an enabler of disruption. The disruption is IoT, and it’s going to be a big one. To prepare for his talk, he did an informal survey of designers at a dozen top companies. Here are some of the things he heard:
Some companies are using FinFET for some chips and FD-SOI for others, depending on the market they’re targeting – either way, the technologies will co-exist. FinFETs were generally chosen for high-density chips from large companies with lots of money; FD-SOI by those who have time-to-market constraints, are looking to differentiate their products, appreciate the much lower NRE* costs, and that are going for power, reliability and analog advantages.
People see a future with FD-SOI – it’s not a one-trick process.
The design community is happy to be able to re-use many of their favorite techniques that were lost after the 130nm node.
Top target markets for FD-SOI are (by far) IoT, automotive and low-power, followed by analog/mixed-signal, networks, RF, low-end products, mobile, peripherals, MPU/GPU, image sensors and rad-hard.
Here are a couple of his slides that sum up the technical and business reasons people cited as reasons for going to FD-SOI:
Dan then made a video recapping his San Jose presentation – it’s awesome – click here to see it.
The ballroom packed right out when GloFo VP Subramani Kengeri took the stage to present, “Enabling Next Generation Semiconductor Product Innovations with 22FDXTM.
In terms of energy efficiency, he explained, 0.4V is the minimum energy point for almost any technology – and FD-SOI gets you 0.4V. He then went on to reiterate the features of GloFo’s 22FDXTM Platform, the industry’s first 22nm FD-SOI:
Ultra-lower power with 0.4 volt operation
Software-controlled transistor body-biasing for innovative performance and power optimization
Delivers FinFET-like performance and better energy-efficiency at 28nm-like cost
Integrated RF: reduced system cost, and back-gate feature to reduce RF power up to ~50%
Integrated eNVM and RF enables lowest cost and smallest form-factor
Post-Silicon Tuning/Trimming for Analog/RF, SRAM and Power/Performance optimization
Enables innovative applications across mobile, IoT and RF markets
70% lower power than 28HKMG, 20% smaller die than 28nm bulk planar
Lower die cost than FinFETs
He then gave lots of technical details (the whole presentation is now available for download from the SOI Consortium website – click here to get it). A key point is that FD-SOI will scale to 7nm. Here’s the slide that says it all:
Also, be sure to check out the Cadence presentation when it’s posted – it looks at the solid design methodology now in place.
Following a brief mea culpa acknowledging that ARM had been missing too long from the FD-SOI table, GM of the Physical Design group Will Abbey made it clear that they are now fully onboard. In his talk, “Realize the Potential of FD-SOI”, he said in comparisons between 22nm FD-SOI and 14nm FinFET, they see a lot of space for FD-SOI. Here’s his summary slide:
They are now looking at ways to further optimize back-biasing to decrease total power in block-level implementations. And yes, he said, you’ll get performance that’s close to FinFET.
Fabless innovator Sigma Designs is focused on the connected home (especially smart TV and media connectivity) and IoT. CEO Thinh Tran presented, “Enabling the Digital Connected World with FDSOI” – you can download it here.
If you really want to optimize for power efficiency, use FD-SOI and run at 0.4V, he advised. “I’m very excited about this,” he told the San Jose audience, adding that, “It’s especially good for RF.” Here’s his slide that explains why:
So, it was a great day in San Jose for 22nm and 28nm FD-SOI. Be sure to keep checking back at the SOI Consortium website, as more presentations will become available in the days to come.
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*NRE = non-recurring engineering. In a fabless scenario, there are NRE for IP and design (engineering costs, up-front and royalty-based IP costs), NRE for masks and fabrication (mask costs, wafer prototype lots, tools costs, probe cards, load-boards and other one-time capital expenditures), and NRE for qualifications (ESD, latch-up and other industry-specific qualifications, as in automotives).