Tag Archive TSMC

Dr. Jean-Pierre Colinge received the 2012 IEEE Andrew S. Grove award at the last ESSDERC-ESSCIRC Conference, for his “contributions to silicon-on-insulator devices and technology.”

IEEE Division I Director, Cor Claeys (right) of imec, honoring Dr. Jean-Pierre Colinge (left) of TSMC for receiving  the 2012 Andrew S. Grove Award for his contributions to SOI. The presentation was made during the 2012 ESSDERC meeting in Bordeaux, France. (Photo Credit: Yann Deval, ESSDERC-ESSCIRC Conference Chair)

IEEE Division I Director, Cor Claeys (right) of imec, honoring Dr. Jean-Pierre Colinge (left) of TSMC for receiving
the 2012 Andrew S. Grove Award for his contributions to SOI. The presentation was made during the 2012 ESSDERC meeting in Bordeaux, France. (Photo Credit: Yann Deval, ESSDERC-ESSCIRC Conference Chair)

Dr. Jean-Pierre Colinge received the 2012 IEEE Andrew S. Grove award at the last ESSDERC-ESSCIRC Conference, for his “contributions to silicon-on-insulator devices and technology.” One of the industry’s most prestigious, the Grove Award is sponsored by the IEEE Electron Devices Society, recognizing “outstanding contributions to solid-state devices and technology.” As noted in the EDS Newsletter, Dr. Colinge’s “…strong actions and enthusiastic beliefs were crucial for supporting the development of SOI technology.” One of the giants of the SOI community, Dr. Colinge is especially heralded in the industry for his seminal and continued work in multigate FETS (aka MuGFETs, a category that includes architectures such as FinFET and TriGate among others). Dr. Colinge and his work have been featured in many editions of ASN. Previous Grove winners with strong ties to the advanced substrate community include Bijan Davari  (IBM, 2010) and Dimitri A. Antoniadis (IBM, 2002).

Breakthroughs at the IEDM

The IEEE’s International Electron Devices Meeting (IEDM) is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here are a few highlights from some of the papers that presented advances in SOI-based devices and architectures at the most recent meeting (December 2008, San Francisco). Read More

Events

Consortium participation in member events and related industry conferences is a terrific way to get the word out.

TSCM Technology Symposiums

The TSMC Technology Symposiums in San Jose and Austin this April represented our first opportunity to participate in a member’s event with our new booth. We received important messages from over 40 companies. The booth traffic make it very clear that there is significant interest in SOI technology, but that we need to continue to work hard to increase visibility and access to IP and tools. Read More

TSMC Reports Industry-Leading Performance

The world’s biggest foundry says its 45nm SOI process technology for the newest generation of high performance CPUs is the best in terms of speed, energy and density in chips using standard nitrided oxide for the gate dielectric.

In terms of speed, energy and density, at TSMC we believe we have developed the industry’s best 45nm SOI process technology among all reported MOSFETs with nitrided oxide. The supporting data was presented by our R&D group at IEDM 2007, in a paper entitled 45nm SOI CMOS Technology with 3X hole mobility enhancement and Asymmetric transistor for high performance CPU application (Samuel K.H. Fung, et al). Read More

SOI By Design

The widening availability of tools and services is good news for designers in the fabless/foundry arena considering the move to SOI.

Leading foundries have made the investments in manufacturing on SOI. Those that have taken the final steps – finalizing electrical characterization, constructing SPICE models, integrating design tools and building libraries – are winning business.

Chartered, for example, is producing SOI-based chips for AMD, the Microsoft Xbox®360, Via, and others in partnership with IBM. TSMC, meanwhile has announced an SOI version of its Nexsys 65nm process technology for next year.

For the high-performance fabless community, IBM itself was the first to open SOI doors to its foundry customers. Ghavam Shahidi, Director of Silicon Technology, IBM Research Division, says they see the full range – from customers that do the whole thing themselves, just getting the IBM-specific SOI IP, to those who essentially hand off the whole project to the IBM services group. Asked how big a challenge the move to SOI is, he says, “It’s not a big deal – it seems scarier than it is.”

As far as those low-power customers worried about the added cost of SOI wafers, he suggests that if they were to consider the broader picture and include things like cooling, they might find it a more cost-effective solution.

In the Flow

Design flow involves a series of iterative steps subject to rules and constraints – many of which are different when devices are built in SOI. SOI-specific IP is needed at each step, especially:

• In support of the logic synthesis tools used to transform the high-level RTL design into a gate-level netlist (which is the collection of “standard cells” and their electrical interconnections specific to the foundry that will do the manufacturing).

• And in the placement and routing tools to layout the chip. Either the design team has to develop SOIspecific expertise (a substantial investment), or license intellectual property (IP) from a third party (the foundry or an IP vendor).

By licensing the requisite IP, designing-in SOI becomes a transparent process. As the designer generates netlists and optimizes placement and routing, the SOI IP is applied via standard EDA tools from companies like Cadence, Synopsys and Magna.

TCAD from Synopsys, for example, can model the SOI technology from the process and device simulation standpoint, so performance of SOI and bulk silicon can be compared before choosing the right technology for the design, says a company representative. Also, engineers can optimize the SOI technology by using TCAD simulation before running costly experimental wafers.

Says Francois Thomas, Europe ICD & DFM Field Marketing Director for Cadence Design Systems, “SOI uses nearly standard processes and design but with better performance. The real difference appears for cell creation, analog simulation and DRC and parasitic extraction.”

SOI IP Vendors

Recently three new SOI IP and design services suppliers have helped bring SOI design to a wider community.

Cell layout of SOISIC standard cells library for 90nm SOI process. (Courtesy of Soisic.)

Soisic. Working with companies that pioneered SOI, Soisic developed extensive design expertise and intellectual property (IP), which is now available to any ASIC designer. For a simple licensing fee, a design team can transparently integrate the SOI-specific design considerations into the design flow – without a special understanding of SOI (things like the history effect, for example) and the differences with bulk. No additional investment in time, training or libraries is needed

Innovative Silicon (ISi). ISi has harnessed the SOI “floating body effect” for memory cells that are twice as dense as existing DRAM and five times as dense as existing SRAM. This proprietary “Z-RAM™” (for Zero capacitor DRAM) technology uses standard SOI logic processes without new materials or extra process or masking steps. For most SoC and microprocessor ICs, this results in SOI being a lower-cost solution than bulk silicon. AMD is the first licensee.

CISSOID. As a fabless player, CISSOID designs custom analog, mixed and digital ASICs, with a specialty in SOI-based high temperature components for oil & gas, aeronautics, space and automotive applications. For low-power and RF applications, CISSOID offers design services, IP development and consulting for optimization of SOI analog and RF circuits.

Mixed Signal & RF Choices

For designers of mixed-signal, analog and RF devices, a growing number of major foundries have been actively promoting their SOI services.

For example, Honeywell offers RF SOI foundry services, supported by a comprehensive tool set and optional design services. The company points out that the SOI-enabled integration of mixed signal and high-voltage applications with complex control functions performed at low power on a single chip ultimately reduces cost.

Others like Atmel promote their SOIbased smart power foundry services for automotive, telecommunications and consumer electronics, noting that using SOI cuts the die-area in half compared to standard bulk technology. The X-Fab foundry service offers SOI-based analog/mixed-signal and MEMS.

All things considered, SOI is now well within the grasp of the greater chip design community.

The SOI version of TSMC’s new 65nm Nexsys Technology

• The SOI version of TSMC’s new 65nm Nexsys Technology for SoC Design will be introduced in 2007.