Tag Archive UCLA

The IEEE S3S Conference Delivered Impressive Technical Content
Posted date : Nov 18, 2013

A view of the Bay from Cannery row, Monterey, CA. The new IEEE S3S conference promised rich content, as it merged both The IEEE In

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!
Posted date : Sep 13, 2013

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa) Last May, we already let you know about the IEEE S3S conference, founded upon

Major paper on porting SOC designs from bulk to FD-SOI released by SOI Consortium
Posted date : Oct 3, 2011

What are you going to do with your SOCs at 20/22nm? The options seem to boil down to just staying on bulk CMOS, or changing to FinFETs or planar,

A Novel Device for Ultra-Low Power & More
Posted date : Jul 30, 2009

Power is the biggest challenge to device scaling for digital applications. Aggressive MOSFET scaling gives rise to many critical challenges, wh