Tag Archive ULP

ARM Steps Up! And More Good News From Consortium’s FD-SOI Symposium in Silicon Valley

ARM is stepping up its effort to support the FD-SOI ecosystem. “Yes, we're back,” confirmed Ron Moore, VP of ARM's physical design group. Thi

Quick Preview of (Great!) FD-SOI Design Tutorial Day (14 April ’17, Silicon Valley)

Would you like to better understand FDSOI-based chip design? If you're in Silicon Valley, you're in luck. On April 14th, the SOI Consortium is or

IEEE SOI-3D-Subthreshold Conference (S3S, Oct. Sonoma, CA) Welcoming Papers til mid-May

The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) will be held in Sonoma Valley, CA 5-8 October 2015. (Phot

ASN Celebrates a Decade of SOI News, Views and Commentary

April 2015 marks the 10-year anniversary of the first ever issue of Advanced Substrate News, aka ASN, covering news and views from the SOI ecosys

Interview (Leti): How a new platform helps designers get the most out of FD-SOI for IoT, ULP

CEA-Leti Clean Room (© Pierre Jayet) A driving force in FD-SOI, Leti recently announced a service called Silicon Impulse®, a new FD-SOI pla

Samsung/ChipEstimate video gives strong plug for FD-SOI

In a new YouTube video, Samsung’s Sr. Director of Foundry Marketing, Kelvin Low, makes a strong case for 28nm FD-SOI, especially for ultra-low-