The SOI Industry Consortium is actively engaged in supporting the industry’s transition to fully-depleted (FD) technologies.
FD technologies offer:
There are two main flavors of FD technologies:
Here are some of the main points we’re making.
Planar FD transistors are cost effective and help close the FinFET gap while maintaining the design infrastructure.
Planar FD significantly simplifies the manufacturing process, resulting in impressive per-die savings as compared to bulk – a point which is now garnering attention.
The value proposition is there: power, performance, cost and variability control. And perhaps most importantly, it’s available at 28nm to the fabless community now, through Consortium members STMicroelectronics and GlobalFoundries.
With oxide-isolated fins, the isolation process is simpler and less expensive. Many of the control issues are improved over bulk isolated FinFETs. The result is faster time-to-market and better power/performance.
With respect to variability control, starting on an SOI substrate enables:
In terms of process, starting on an SOI wafer as opposed to bulk means:
With SOI, dielectric isolation is superior. This results in:
So when considering the bottom line, FinFET on insulator (compared to FinFET on bulk) is:
There are at least 3 major substrate vendors supporting the transition to fully-depleted technologies. Their combined output will easily provide the required industry volume, and can be expanded if needed.
IDC predicts that worldwide smartphone shipments will reach over 1.16 billion in 2016. The processors will require about 1.3 million wafers/year. (See figure.) The combined capacity of the existing suppliers is 2.3-2.4 million wafers/year by early 2014. They have indicated that additional factory capacity can be put in place within a 12 month window, so incremental capacity can quickly reach 3 million wafers/year – more than enough to meet projected demand.
At the SOI Industry Consortium, we are extremely pleased with the traction we’re getting. With the first FD-SOI products hitting the shelves, we think 2013 will be an exciting year.
FinFET technology promises continued scaling of CMOS technology via the potential to reduce (deleterious) short- channel effects. Realization of this potential is highly dependent on the ideality of the fin structure and, in particular, the uniformity of fin width and impurity doping. The fin isolation technology has a strong impact on within-fin uniformity and variability, and can compromise power, performance, and manufacturability.
Here we briefly explore several important aspects regarding the benefits of employing Fin-on-Oxide (FOx) isolation of the active FinFET channel region from the substrate semiconductor over that of first-generation bulk FinFETs, and examine how FOx as enabled on an silicon-on-insulator (SOI) wafer is well-positioned to deliver optimal FinFET value in 2nd Generation CMOS technology.
In a bulk a FinFET process, fins are formed in bulk silicon, an isolation oxide (SiO2) is deposited in the trenches between fins, and then etched back to expose some portion of the fins, thus defining the baseline active fin height.
Ideally the fins formed would be vertical and of uniform width (TFIN) to best realize uniform FIN turn-on (from top to bottom of the fin). Practically, however, there are two process issues that drive a need to taper the fins, resulting in ‘triangular’ shapes. The first issue is that the cavities between fins must be filled without forming voids, which necessitates a fin sidewall that is less than 90 degrees. Such voids, if formed, are capable of killing yield (such voids can subsequently fill with either source/drain materials or gate materials, causing short-circuits). The second issue is driven by the need to clear the sidewalls of the fins following (dummy) gate formation, prior to source/drain epitaxial growth. These spacers must be removed from source and drain regions of fins by an anisotropic etch and hence more gently sloped fins, require less over-etch. Some over-etch is always required since any remaining spacer material on an occasional fin can block the formation of the source and drain regions, again killing yield. Extension of over-etch times erodes the isolation oxide adjacent to source and drain fin regions (the channel region is protected by the dummy gate) and hence (vertical) misregistration of the source/drain regions to the gate is worsened, requiring further steps to avoid sub-channel leakage in the fin. The net of this is that a bulk fin employing well/ junction isolation brings with it some intrinsic compromises in fin shape/morphology.
The bulk FinFET includes a ‘sneak path’ from drain to source in a portion of the fin that extends below the channel. Illustrated in Figure 1 are three ‘alignments’ of importance to well-isolated FinFET designs.
Ideally, the source/drain depth, YSD, the channel-stop depth, YCS, and the gate-edge depth, YGE, would be identical with an abrupt doping step in the fin, just below the gate, to cut off the ‘sneak path.’ Practically, such a structure is not possible, and so, even for an ideal, vertical fin shape, doping in the sub-fin must be sufficiently high to cut off this leakage. In this case one could simply dope the fins uniformly; the doping level required is greater than that needed to achieve a given channel leakage without the sneak path. Penalties for product design, illustrated in Figure 2, ensue.
The maximum operation voltage is limited by maximum allowable electric field in the gate dielectric. Higher doping in the channel results in higher electric fields in operation in a bulk fin, and hence there is an associated reduction in Vmax also illustrated in Figure 2. Additionally, VT variations are increased by this higher doping, and Vmin is increased, for SRAM and other matching-critical circuits. Both ‘Turbo-mode’ performance and low-power mode operation suffer in a bulk-isolated FinFET.
Thus far we have taken the case of ideal fin morphology; in practice, bulk-isolated fins present a fin channel with a wider base and the resulting poor gate control requires an even higher doping in this region. The doping at the base of the fin must be sufficient to elevate the local VT by 100-200mV above that of the upper, narrower, portions, in order to avoid excessive device leakage. The output conductance is severely degraded by the delayed, soft turn on of the composite fin. Effective drive current is lost, in this example on the order of 15%, and additionally analog-like high-speed circuits, such as High-Speed I/O are compromised.
Whether on bulk or SOI, FinFETs introduce one fundamentally new behavior for CMOS products, that of (active) fin height (Hfin) variation. In a FinFET transistor, the WEFF varies nearly in proportion to Hfin. Large (wide) transistors will vary in drive strength nearly as much as narrow transistors, since the ‘wide’ FETs simply consist of a larger number of the same base fin. As Hfin varies from die-to-die due to manufacturing variations, the WEFF of every transistor varies by the same percentage, not the same number of nanometers, as in planar CMOS. This means that active power and performance of a product can be strongly modulated by Hfin, and the tolerances of the bulk manufacturing process can be driven by many challenging-to-control factors, such as across-wafer uniformity, process chamber uniformity, and local design-driven density and proximity issues. The die-to-die variation can appear as an Fmax/Power CLY loss.
While dielectric isolation has been demonstrated on bulk wafers, these schemes continue to lack Hfin control and add cost to the bulk integration for FinFETs. A FinFET process based on an SOI wafer is cost neutral compared to a bulk-isolated Fin with the additional SOI wafer cost easily equaled by the additional bulk process complexity.
SOI offers ultimate Hfin control, with the SOI layer itself defining Hfin. No pattern sensitivities enter, as the active silicon layer is formed unpatterned across the entire substrate. Isolation is automatic and no extra process steps, beyond those required for the transistor formation, are required. Thus within-die and die-to-die variation of Hfin is much less than any currently known alternative, leading to the lowest Vmin, power, and highest Fmax, and CLY for FinFET CMOS.
Strain: Mechanically straining the silicon channels can enhance both hole and electron mobility. Direct techniques for imparting fin strain apply equally to fins on either substrate. One technique employed, embedded SiGe for pFETs, does present a small gain in attainable strain of up to 6% in bulk-fin pFET drive current, amounting to a 3% decrease in a CMOS critical path delay. This gain for the bulk case is, in reality, eroded, if not reversed, by an increase in leakage current from the source/drain region recess beneath the gate, required to realize the added strain. The final result is that an academic gain of up to 3% might be afforded a bulk fin over its SOI counterpart, but when other strain techniques and short-channel degradations are considered, even this benefit vanishes.
Self-heating in SOI FinFETs is very similar to that in planar SOI MOSFETs, and as such, the issues and solutions are well understood at a practical product-applications level. For digital circuits, self-heating is not a consideration, as the short-transient energy dissipated from a single transition is absorbed by the heat capacity of the device with a negligible temperature rise. For circuits in which duty factors are sufficiently high, well-established CAD techniques from planar SOI offer solutions. A narrow sliver of silicon connecting a bulk FinFET to the substrate does reduce the degree of self-heating, but similar CAD requirements in product design remain. Other aspects surrounding self-heating include effects on device and interconnect aging, and here again, the techniques practiced over several generations of planar SOI enable design capability to assure the required product reliability in the field.
Wafer cost and supply: SOI FinFET technology enables a competitive high-volume presence in the market. The steps required to isolate fins on a bulk substrate add considerable complexity and process cost which easily negates any savings in initial wafer cost. Furthermore, the simpler process with SOI FinFETs results in shorter turn-around time. The reduced variability on SOI returns improved yield, and recent announcements by major wafer suppliers have assured a volume supply chain.
In addition to the quantitative advantages of SOI-based FinFET described above, the very nature of the near-ideal isolation provided opens many doors to diverse applications. IBM has enjoyed a significant advantage in processors through the integration of embedded DRAM, enabled by SOI isolation, providing 3X net memory density advantage and similar power reduction. RFCMOS, now exploiting SOI in mature nodes, will continue to find high value in SOI FinFETs due to lower parasitic capacitances, reduced (inductive) substrate losses, and radically lower substrate-driven harmonic generation (and other product mixing). A wide range of voltage islands are naturally available, both above and below substrate/ground, without the complexity of triple wells and the restrictions/penalties associated with latch-up avoidance. Automotive, and other very high-temperature environments present no barrier in SOI-based FinFETs.
The value proposition of SOI presented in PDSOI becomes even stronger in FinFET technology, as clearly described above. Furthermore, the design drawbacks of non-standard timing tools and added cost, which presented some barrier in PDSOI vanish as we migrate to FinFET technology, and portability of products from bulk to SOI FinFET designs is very high. As SOC FinFET products are introduced, it is expected that the benefits of dielectrically isolated fins, and in particular, the SOI implementation for this isolation, will prove a clear winner in the market place due to lower variability, lower power, simpler designs and greater flexibility for integration of multiple product needs on chip.
To drive the competitiveness of PCs, smartphones and other leading-edge devices, the electronics industry has relied for decades on the continued miniaturization of the multitude of transistors integrated in the chips at the heart of those products. However, at the tiny dimensions transistors are reaching today, conventional technology is becoming ineffective to satisfactorily combine higher transistor density, meaningful performance gains and low power consumption.
To continue scaling CMOS technology, new approaches are needed and the industry is turning to ultra-thin body, “fully depleted” (FD) transistors. These may retain a planar architecture (Fig. 1b) or go tri-dimensional (Fig.1c), in which case current flows in vertical ‘fins’ of silicon.
In both cases, in contrast with traditional technology, the current between source and drain is only allowed to flow through a very thin silicon region, defined by the geometry of the transistor. In addition, such transistors can eliminate or alleviate the need for implanting “dopant” atoms into their channel.
The physics of FD transistors allows their behavior to be greatly improved – making it possible to continue creating more complex chips with better performance and, most importantly, with power consumption kept under tight control.The semiconductor industry is introducing planar FD (also referred to as FD-SOI) starting at the 28nm node, with first IC product samples scheduled for the end of 2012. Tri-dimensional FD or FinFET, on the other hand, is expected below 20nm in foundries.
With FD technology, either planar or tri-dimensional, the transistors are either necessarily or advantageously fabricated on innovative silicon-on-insulator (SOI) starting wafers. These wafers consist of a very thin layer of crystalline silicon, separated from a silicon base by a high-quality (and optionally ultra-thin) oxide. Soitec’s Smart CutTM technology is used to produce them and is licensed to third-parties to ensure multi-sourcing options.
Top silicon and buried oxide requirements (thickness, uniformity, etc.) are different for the planar and FinFET implementations of FD transistors. Two different wafer product lines are available to serve the needs of these two technology flavors.
Planar FD technology puts tight requirements upon starting wafers to deliver all its benefits: for example, top silicon layer thickness must be uniform to just a few Angstroms. Today, Soitec’s FD-2D product line meets these needs in a cost-effective way and makes planar FD technology a reality.Figure 2 outlines the structure of a transistor fabricated from an FD-2D wafer. For the 28nm technology node, the buried oxide thickness has been set to 25nm; the ultra-thin top silicon allows fabrication of transistors with 5nm to 8nm silicon under the gate. Future generations can leverage even thinner buried oxide layers, contributing to making this technology scalable to subsequent nodes.
By enabling a planar implementation of fully depleted technology, these wafers offer the opportunity to access the benefits of FD today – there is no need to anxiously await FinFET and the 16nm/14nm technology node. Adopters of planar FD are announcing very substantial performance and leakage gains as well as impressive improvements of energy efficiency, along with exceptional performance maintained at very low power supply [Ref.1-3].
Owing to the great compatibility of planar FD with conventional CMOS, designers retain the flows and tools they would use with the latter. Furthermore, chip manufacturers use the same production lines as well as extremely similar process steps. Finally, different studies indicate that the cost of ownership of chips based on planar FD is extremely competitive compared to any alternative.
A FinFET transistor consists of one or several fins of silicon, electrically isolated from the substrate, around which the gate wraps.One solution (Figure 3a) to manufacture FinFETs consists of starting from a traditional bulk silicon wafer and completely handling fin creation and isolation through the CMOS process. The alternative (Figure 3b) is to start from a “FinFET-friendly” wafer such as Soitec’s FD-3D, which pre-defines some of the fin characteristics and, with its buried oxide, natively embeds the electrical isolation, thus simplifying the CMOS process.
Specifically [Ref. 4-5], FD-3D wafers help obtain clearly defined and reproducible fin height and width, consistent alignment of gate, source, drain and channel, and provide optimal isolation of each fin. In addition, it is possible to implement undoped fins if desired – thus cutting variability related to random dopant fluctuations.
Overall, and especially as dimensions will continue to shrink beyond the 16nm node, FD-3D wafers offer to facilitate control over key parameters of FinFETs as well as simplify the fabrication process. They represent an opportunity for chipmakers to make the most of FinFET technology in terms of power/performance ratio and leakage power at chip level. They are also a worthwhile proposition to reduce the industrialization challenges and optimize the total cost of ownership.
Looking beyond the 10nm node, technology based on germanium and III-V compounds is being actively researched. In parallel, the transition of leading-edge chip production to 450mm diameter wafers is expected for the end of this decade.
In this context, the Smart Cut™ layer transfer technology for manufacturing innovative wafers may again prove extremely valuable by enabling independent control over various optimization knobs. For example, transferring a thin layer of high-quality, optimized III-V material onto a low-cost handle wafer (silicon or other), with an optimized interfacing layer, could be an interesting option.
Fully depleted silicon technology is coming. The question is how fast and how easily this transition can be accomplished: innovative wafers provide part of the answer.
With FD-2D, they enable a planar implementation, providing the semiconductor ecosystem with an early and low-risk path towards optimal performance and power efficiency across all use cases, as soon as the 28nm node.
With FD-3D, they can help efficiently address some key challenges of FinFET technology and make the most of it.
Looking further ahead, the Smart CutTM technology will continue to simplify the implementation of the next silicon technology breakthroughs.
[Ref.1] White Paper, “Planar fully depleted silicon technology to design competitive SOC at 28nm and beyond”, STMicroelectronics – http://www.soiconsortium.org/about-soi/white-papers.php
[Ref.2] ST Ericsson Technology Blog, May 2012: “FD-SOI: A process booster for ST-Ericsson’s next generation NovaThor – Part 2”, http://blog.stericsson.com/blog/2012/05/st-ericsson-general/fd-soi-a-process-booster-for-st-ericssons-next-generation-novathor-%E2%80%93-part-2-2/
[Ref.3] “MWC ST-Ericsson Media & Analyst Briefing”, February, 2012 – http://www.stericsson.com/investors/Analyst-Event-Presentation-MWC-12.pdf
[Ref.4] « SOI Value in IBM Silicon Technology », Oct.2011 – http://www.gsaglobal.org/3dic/docs/20111019_IBM_SOI_Value_GSA.pdf
[Ref.5] “SOI versus bulk-silicon nanoscale FinFETs”, Jerry G.Fossum et al., SSE Volume 54, Issue 2, Feb. 2010.
In a recent study entitled Economic Impact of the Technology Choices at 28nm/20nm, International Business Strategies (IBS) has found that those companies choosing FD-SOI at 28nm and/or 20nm should benefit from substantial savings in cost-per-die (see figure).
For a technology to be utilized in high-volume production, costs must be lower than previous generations of technology. The industry thus faces a critical juncture in the shrink from 28nm to the nodes around 20nm (the precise dimensions of which vary by foundry). Making the wrong technology decisions at ~20nm can cost wafer manufacturers and fabless companies billions of dollars. It is therefore appropriate to analyze the cost factors for the different versions of 28nm as a baseline.
Multiple factors need to be considered with the migration to ~20nm, and the highly visible experience to date in attaining high yielding, volume production on 40nm and 28nm from the industry’s largest players provides visibility into what is likely to happen at 20nm bulk.
IBS has been in the business of modeling and analyzing the impact of technology choices for clients in the semiconductor and related industries for over 20 years. Our robust approach has stood the test of time, enabling us to predict the economic impact of such decisions with a high degree of accuracy.
For the purposes of our analysis, we consider die sizes of both 100mm2 and 200mm2. The flavors we considered are for high-performance (HP) and low-power (LP) chips. The technology options at the 28nm node are high-k/metal-gate (HKMG) bulk CMOS vs. FD-SOI. For the ~20nm node, we add FinFET to the analysis.
At the 28nm node, if you only look at the processed wafer cost, the FD-SOI solutions are roughly 7% higher. However, yield issues and the net die/wafer at 28nm have a major impact on the bottom line. When defect densities and parametric yields are factored in, the FD-SOI solution results in a lower per-die cost: from 8% lower for the smaller, low-power chips, to 18% for large, high-performance chips.
At 20nm, however, the FD-SOI processed wafer cost is less than both bulk CMOS and FinFET processed wafers. The FD-SOI processed wafer cost advantage is then massively increased when yields are factored in.
Once ~20nm bulk FinFETs have matured in Q1/2016, FD-SOI will still offer comparative per-die savings of 50-60%.
Power/performance characteristics of FD-SOI will be 30% to 40% superior to bulk HKMG CMOS at 20nm. Analog porting of FD-SOI will be easier than with the other options because of the superior sub-threshold characteristics.
Today, FD-SOI is the only technology that can operate safely in the 0.6V to 0.7V range at 28nm. While there is some reduction in performance, operating power is reduced, giving a very compelling performance-power advantage against other technologies.
Although the real competition is likely to be between FinFETs and FD-SOI at 20nm, FinFETs are a new technology (from a high-volume production perspective), with significant cost penalties even in Q1/2016.
Bulk HKMG CMOS will have low parametric yields at 20nm. A major source of yield loss for bulk CMOS is that of random dopant fluctuations from transistor implants. These implants are not required for FD-SOI. ~20nm FinFET structures will be high-cost to manufacture, and parametric yields will be low.
The time to reach defect density-related yields with allowance impact of parametric yields is estimated to be 12 to 18 months for FD-SOI versus 24 to 36 months for FinFETs.
So compared to bulk CMOS or FinFET, the FD-SOI option cuts ramp time by as much as half.
The faster ramp-up of wafer volumes combined with more predictable yield ramp-up provides additional cost benefits in using FD-SOI over other options at 20nm.
There is ongoing work to assess the further scalability of FD-SOI beyond 20nm to ~14nm and the initial results from IBM and Leti look promising.
For the purposes of this analysis, the processed wafer costs are derived from experience with leading foundries, for their costs in Q1/13 with eight metal layers (8LM). (Selling prices of processed wafers will of course be higher and will include the gross profit margins of the foundry vendors.) The processed wafer costs include $500 for the ultra-thin SOI wafer used in the FD-SOI process, and $129 for the bulk wafer used in bulk CMOS and bulk FinFET technologies. (While there is the expectation that the SOI wafer prices will be reduced in the future, this is not built into our analyses.)
We assume a high-volume production with utilization rates of about 95%. The bulk version assumes three threshhold voltages (Vt) in the core of the chip, and takes into account support for SRAMS and interfaces. The FD SOI cost is based on 1Vt level for the core and use of body biasing. Body biasing can give two additional Vt levels in the core, which is equivalent to bulk CMOS design options.
Wafer and die costs vary at different stages of maturity. For FinFETs, for example, the cost takes into account the relatively long time for metrology checking in the process and also the manufacturing complexity related to the FinFET structures.
CMP is offering multi-project wafer runs of ST’s 28nm FD-SOI technology on Soitec wafers with Leti models. It’s the same technology that GF will be rolling out in high-volume next year. This article details how it works, and what it includes.
What would a port to 28nm FD-SOI do for your design? A recent announcement by CMP, STMicroelectronics and Soitec invites you to find out. Specifically, ST’s CMOS 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) process – which uses innovative silicon substrates from Soitec and incorporates robust, compact models from Leti – is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP (Circuits Multi Projets®). ST is releasing this process technology to third parties as it nears completion of its first commercial FD-SOI wafers. What you can get from CMP is the same process technology that will be available to all at GlobalFoundries in high-volume next year.
The CMP multi-project wafer service allows organizations to obtain small quantities of advanced ICs – typically from a few dozen (for a prototype, say) to over a hundred thousand units (for low-volume production). CMP is a non-profit, non-sponsored organization created in 1981, with a long history of offering SOI and other advanced processes. It offers industrial quality process lines – with industrial-level, stable yields. Headquartered in Grenoble, France, CMP has over 1000 clients in 70 countries.
The cost of ST’s 28nm FD-SOI CMOS process at CMP has been fixed at 18,000 €/mm2, with a minimum of 1mm2. At this point in scaling, that gets you about two million gates – about eight million transistors. So the pricing is very aggressive for an advanced technology node – and it comes down if you get more than 3mm2, and even more if you get >15mm2, Kholdoun Torki, CMP Technical Director explained to ASN.
Dr. Torki was kind enough to elaborate a bit on the particulars for us. Here’s what he says. The ST design kit contains a full-custom part, and standard-cells and I/O libraries with digital design-flows supported under Cadence Encounter and Synopsys Physical Compiler. The design-kit is from ST Front-End Manufacturing and Technology, Crolles. CMP delivers this design-kit under NDA.
Devices are supported for UTSOI (ultra-thin SOI) models, which were developed by and are the property of Leti.
The UTSOI model is available under Eldo from Mentor and Hspice from Synopsys. It is also expected to be available for Spectre (Cadence) and for Golden Gate and ADS (Agilent) within the next few months.
CMP provides the first level support (installation, and general questions on the use of the kit). Multi-Projects Wafer runs are organized at ST Crolles. For low volume production, a quote is issued on a case-by-case basis, on request.
The ST 28nm FD-SOI offering has a true 28nm BEOL metallization with .1µ metal pitch, says Dr. Torki.
CMP also has offered the Leti 20nm FD-SOI R&D process since 2010. (In fact for those looking even further ahead, Leti has predictive model cards down to 11nm.) It is expected the 20nm FD-SOI process from ST, incorporating strategic technology from Leti, will be available from CMP towards the end of next year, although the exact date has not yet been fixed.
In Multi-Project Wafer runs, costs are shared (and reduced) because the reticle area is shared across customers. CMP offers one-stop shopping, including:
Last year (2011), CMP handled 273 circuits, including prototypes, low-volume production runs and industrial applications.
For organizations like the 77 customers in 23 countries using 28nm bulk CMOS through CMP’s program, migrating from 28nm CMOS bulk to 28nm FD-SOI will be seamless, says Dr. Torki. There are no disruptions in process or design. There are the same layer numbers and names, so they can load a bulk design directly into an FD-SOI design environment. They use the common design-rules platform (ISDA alliance design-rules), and bulk devices can be co-integrated with FD-SOI devices as needed.
These are real, leading edge chips and circuits we’re talking about. Here’s what you get:
The 28nm FD-SOI standard-cells, IO cells and related IP are all from ST. The CORE cells Libraries include:
The IO cells Libraries include:
You can find more details at the CMP website, or from the paper Dr. Torki presented at the 2012 SOI Conference.
So this represents a real opportunity. Universities, often doing important research for industrial partners, have long known the value of using services like CMP’s. But with this latest ST-CMP-Soitec announcement, the fabless world can do more than kick the tires – they can take 28nm FD-SOI for a real test drive.
FD-SOI promises an extremely cost-effective, performance-enhanced, power-miser of a chip. Wouldn’t you like to give it a try?
It’s a bright green light from the world leaders in SOI wafer capacity. Soitec, the world leader in SOI wafer production, and long-time partner Shin-Etsu Handatai (SEH), the world’s biggest producer of silicon wafers, have extended their licensing agreement and expanded their technology cooperation.
SEH is a $12.7 billion company, supplying over 20% of the world’s bulk silicon wafers. SEH’s relationship with Soitec goes way back: they were one of the original corporate investors back in 1997, and the first to license Soitec’s Smart CutTM technology for manufacturing SOI wafers.
With its 300mm SOI wafer production fabs in France and Singapore, Soitec has an expandable installed industrial base of two million wafers per year.
As Horacio Mendez, Executive Direct of the SOI Consortium told ASN, “This is a very significant announcement. The substrate supply chain is fully engaged: we have multiple independent suppliers that can clearly meet the market demands for all key sectors, including mobile devices. As the advanced technology nodes ramp, the wafer production is in place; and very importantly, the capacity is expandable to provide maximum flexibility to customers.”
SEH has been manufacturing standard SOI wafers using Smart Cut technology for years. And last year, the company said it had completed development of its ultra-thin BOX (aka UTB — the wafers used for planar FD-SOI) substrates. Nobuo Katsuoka, director of the SOI program at SEH, recently told Semiconductor Manufacturing & Design, “SEH is delighted to deliver the products on request.”
Wafers for FD-SOI (a “planar” “2D” technology) have Angstrom-level uniformity in their ultra-thin layers – so it’s excellent news that the the industry’s two leaders are both supply sources.
SOI wafers for FinFETs (a “vertical” or “3D” technology, for which the top silicon and insulating BOX layer don’t have to be ultra-ultra-thin) have also long been available from Soitec, SEH and other sources.
With respect to this announcement, SEH’s Katsuoka said, “We are very excited about the business opportunities for SOI products, and we look forward to working with Soitec to extend the global supply chain for new products, such as FD-SOI and SOI for FinFETs, which are showing potential benefits in mobile and embedded applications. Our relationship with Soitec has been a very positive and fruitful one, and we are excited to extend that collaboration. The unique features of Smart Cut will enable our two companies to jointly improve global output for existing and new SOI products.”
As Steve Longoria, SVP of WW Business Development at Soitec, told ASN, “The wafer is the front end of the manufacturing process. This announcement is a proof point of new energy for robust, multi-source supply for impending high-volume demand.”
The newly announced Soitec-SEH agreement also extends the companies’ commitment to wafers for a broad-range of areas. For example, there are major market opportunities in SOI for RF devices, power, MEMS/sensors, photonics and more.
The agreement also extends to R&D for technologies of the next wave. We might think of Smart Cut as an SOI technology, but in fact it’s really a manufacturing technology that can be applied to a huge range of wafer materials. As a result of the extended agreement, SEH will continue to use Soitec’s industry-defining Smart Cut technology to manufacture SOI wafers, and now will be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), which will allow SEH to further expand its scope of applications.
So with an abundance of opportunities, a robust multi-source supply chain for the front end of the chip manufacturing process, top-quality wafers that enable savings and efficiencies – in short, better end-user value – it’s all systems go for high-volume demand.
At the SOI Consortium’s 6th FD-SOI workshop (held just after ISSCC), excellent talks were given by STMicroelectronics, IBM, ARM, Leti, Soitec, Accelicon and UC Berkeley. Most of the presentations are freely available for downloading from the SOI Consortium website.
As Horacio Mendez, Executive Director of the SOI Consortium concluded, this workshop was great. “We’ve been offering these workshops for over two years,” he said. “The community has taken Fully Depleted SOI from a technical advantage in the lab to a technical advantage on mobile products (as presented by ST). The cost, power, performance and manufacturability of FD-SOI is a significant driving force.”
Planar fully depleted silicon technology to design competitive SOC at 28nm and beyond [STMicroelectronics, Soitec]
This document considers the challenges to obtain competitive silicon technology for the upcoming generation of System-On-Chip ICs. The full document can be freely downloaded from the Consortium website. Also, please see pages 1-3 of this edition of ASN for highlights and excerpts.
20nm FD-SOI logic evaluation model cards are now available through the SOI Consortium in cooperation with Accelicon/Agilent. An NDA is required. Please contact Horacio Mendez, Executive Director of the SOI Consortium at email@example.com to get a copy.
[aside]STMicroelectronics, IBM, ARM, GLOBALFOUNDRIES, Soitec and other leading semiconductor companies in the SOI Consortium recently participated in a benchmarking study. Each tackling different aspects, they detailed the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. The joint research was performed by using an FD-SOI process to fabricate 28nm chips. Test results on these chips were in line with predictions from computer-based models previously developed to benchmark FD-SOI device performance, confirming the models’ reliability – key for both designers and foundries. This article looks at some of the implications.[/aside]Chipmakers constantly have to manage risk. Generally it is considered sensible not to try to engage in more than one major change at a time – geometry shrinks already introduce enough challenges. So planar FD-SOI devices, which use proven, well-understood design and manufacturing techniques should be particularly appealing for both current and upcoming nodes.
Horacio Mendez, executive director of the SOI Industry Consortium noted that FD-SOI also represents a low risk in terms of manufacturing for upcoming nodes.
“FD-SOI’s ability to accommodate planar architectures presents much lower manufacturing risk than FinFET,” he said. “This makes FD-SOI an easy-to-implement solution for cost-sensitive applications that require performance and low power consumption in standby and active modes, including mobile electronics such as smart phones and tablet computers.”
For many if not most designers, extending the life of existing planar bulk CMOS designs will make good sense. With a planar FD-SOI solution, these existing designs and related IP can be migrated in a comparatively straightforward way, producing chips that benefit from the intrinsic advantages of fully depleted wafer technology with minimal risk and lower cost.
The SOI Consortium study also points out that FD-SOI is compatible with all power-reduction techniques used by IC designers – and can even boost the efficiency of some. Furthermore, FD-SOI can accommodate some design tweaks (not available with FinFET designs), such as leveraging dynamic back-bias to increase performance or reduce leakage power in some applications.
Fully depleted transistor architectures such as Planar FD-SOI, FinFET (which is also a fully-depleted technology, and can be on SOI or bulk) and other Multi-gate (MuGFET) devices each having compelling advantages in their favor.
Designers are considering the power and performance needs of their applications, assessing the manufacturing risks and evaluating the importance of extending current IP – which makes FD-SOI a very strong contender for current and upcoming nodes.
The Consortium study indicated that FD-SOI handily beats traditional planar CMOS devices built on bulk-silicon substrates even at 28nm.
The Consortium benchmarked 28nm bulk vs. 28nm FD-SOI, so they could make comparisons in silicon of representative IP blocks, such as ARM cores and memory controllers. Here are some of the potential implications of what they’re saying.
• Peak performance is comparable with the much leakier ‘General Purpose’ technology flavors, at better dynamic power, and dramatically better leakage power, even lower than what ‘Low Power’ technology flavors achieve.
FD-SOI peak performance is comparable to that of GP, and significantly better than LP (low power) technologies.
The dynamic power gap, however, gets better and better as you can reduce the power supply voltage (i.e. when you’re not shooting for extreme operating frequency) — because the drop in performance when the supply voltage (Vdd) is lowered is much less marked with a fully-depleted technology.
The trick is, 1) not all portions of an SOC need highest possible performance and 2) even those that do need that performance only need it a fraction of the time — when running very demanding scenarios. So when you consider the dynamic power at chip level across use cases, then your overall dynamic power is dramatically better.
This also means, if you have a chip in bulk technology (LP or G) that runs fine in terms of performance but you’d like to cut its total power, then planar FD-SOI is a great solution.
• The feasibility of running all digital device designs, including SRAMs, at very low Vdd (e.g., 0.6 volt).
One of the great problems of traditional bulk CMOS is that SRAM memories quickly become unstable if their Vdd is reduced. Being unable to reduce Vdd, you cannot lower their power consumption even when you don’t need maximum access speed from them. By contrast, fully-depleted technologies enable you to operate both logic and SRAM at reduced Vdd.
• The opportunity for substantial power savings of up to 40 percent by using a lower Vdd to reach the same target frequency.
• Much better performance than bulk CMOS when the power supply (Vdd) is lowered. At 0.6V, critical paths on 28nm FD-SOI circuits were more than 50 percent faster than the General Purpose technology and more than twice as fast as Low Power technology.
With respect to dynamic power consumption (the power lost in switching), it’s proportional to the square of Vdd. So if you reduce Vdd and still hit the target frequency, you get a bigsavings in dynamic power consumption.
Leakage power – AKA static power – is the power lost when sub-threshold currents wander away even when the transistor is off. It’s the major cause of wasted power in standby mode. The Consortium study found that FD-SOI does better than both G and LP bulk technologies at 28nm in terms of leaky transistors.
The study provided silicon proof that FD-SOI handily beats traditional planar CMOS devices built on bulk-silicon substrates even at 28nm.
Armed with the information from the 28nm bulk vs. FD-SOI benchmarking study, the SOI Consortium members then did new benchmark simulations at the 20nm node. This confirmed the trends they saw in silicon at 28nm. When comparing FD-SOI technology to bulk technology specifically intended for System-on-Chip (SOC):
Here’s the graphic that says it all. Follow the suggestions in the annotations to see how the power vs. performance trade-off works.
To use this graph: pick any point on the lower, bulk line, then move horizontally to the left to see how much less power it will take to hit the same frequency with FD-SOI. By adjusting Back Bias, FD can be changed from: High Performance Mode TO Leakage Saving Mode.
Comparing SOC power and performance for planar FD-SOI vs. standard (planar) bulk silicon design at the 20nm node.
(a) Reverse back-bias allows you to cut leakage, here by a factor of 10
(b) This line is 20 nm FD-SOI with back biasing
(c) Or with back-biasing FD-SOI, you can hit over 269 MHZ using 120 mW at 1 V power supply
(1) This line is 20 nm Bulk
(2) This line is 20 nm FD-SOI
(3) Bulk takes over 130 mW to hit frequency of about 223 MHz with supply voltage of 1 V
(4) To hit the same with FD-SOI takes just over 100 mW and a supply voltage of just 0.9 V
(Courtesy: SOI Consortium)
Editor’s note: Special thanks to the SOI design experts who helped with the explanations in this article.
Work at Leti shows that strain is an effective booster for high-performance at future nodes.
The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past.
As illustrated in Figure 1, strain can be incorporated at various places in the transistor:
First, it is worth noting that local stressors are often more effective on FD-SOI than on bulk at a given geometry because of the mechanical properties of the buried SiO2, which is less stiff than Si.
We have assessed different boosters on the FD-SOI architecture. The results are summarized in Figure 2.
For NMOS, one can see that sSOI is the more promising stressor with an ION improvement of 20-35 % for wide devices; and, it can increase up to 50 % for W = 50 nm narrow transistors . Our preliminary results let us predict a better scalability for sSOI than for t-CESL or SMT. Moreover, the compatibility of sSOI was already proved (even if the ION-boosts are not always totally additive) with t-CESL for NMOS and with rotated substrates, e-SiGe, SiGe channels and (110) substrates for pMOS.
For pMOSFETs, there are several options to enhance the ION, the simpler being the 45° rotated substrates with a 8 % boost and r-SiGe with a 18 % improvement by an access resistance reduction (37 % if a strain can also be generated into the channel). Once again, the scalability of the global boosters is certainly better than for the local ones (c-CESL and e-SiGe).
In conclusion, thanks to all the experiments already run, we are confident in the fact that strain can be incorporated in the planar FDSOI architecture, thus boosting performance even further at 20 nm and beyond.
NOTE: This article was adapted from the Leti presentation, “FD-SOI strain options for 20 nm and below”, given at the SOI Consortium’s 6th FD-SOI Workshop. The complete presentation is available at www.soiconsortium.org.
– – – – –
 C. Fenouillet-Beranger, L. Pham Nguyen, P. Perreau, S. Denorme, F. Andrieu, O. Faynot, L. Tosti, L. Brevard, C. Buj, O.Weber, C. Gallon, V. Fiori, F. Boeuf, S. Cristoloveanu,
T. Skotnicki, “Ultra compact FDSOI transistors (including Strain and orientation) processing and performance”, ECS Transaction, 2009.
 S. Baudot, F. Andrieu, O. Faynot, J. Eymery, “Electrical and diffraction characterization of short and narrow MOSFETs on Fully Depleted strained Silicon-On-Insulator
(sSOI)”, Solid State Electronics, 2010.
 F. Andrieu, C. Fenouillet-Beranger, O. Weber, S. Baudot, C. Buj, J.-P. Noel, O. Thomas, O. Rozeau, P. Perreau, L. Tosti, L. Brevard, O. Faynot, “Ultrathin Body and BOX SOI
and sSOI for Low Power Application at the 22 nm technology node and below”, invited talk at SSDM, 2009.
 S. Baudot, F. Andrieu, O. Weber, P. Perreau, J.F. Damlencourt, S. Barnola, T. Salvetat, L. Tosti, L. Brévard, D. Lafond, J. Eymery, O. Faynot, “Fully-Depleted Strained Silicon-
On-Insulator p-MOSFETs with Recessed and Embedded Silicon-Germanium Source/Drain”, 2010.
 F. Andrieu, T. Ernst, O. Faynot, Y. Bogumilowicz, J.-M. Hartmann, J. Eymery, D. Lafond, Y.-M. Levaillant, C. Dupré, R. Powers, F. Fournel, C. Fenouillet-Beranger,
A. Vandooren, B. Ghyselen, C. Mazure, N. Kernevez, G. Ghibaudo and S. Deleonibus, “Co-integrated dual strained channel on fully depleted sSDOI CMOSFETs with
HfO2 /TiN gate stack down to 15 nm gate length”, IEEE SOI Conference, p. 223-5, 2005.
 T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, S. Takagi, ”(110)-Surface Strained-SOI CMOS Devices”, IEEE Transaction of Electron Devices, 52, 3, p.367, 2005.