ST looks at a hybrid FD-SOI/bulk approach to SOCs for multimedia.
The heterogeneous nature of System-on-Chip (SOC) design for the next generations of wireless, high-performance, low-power multimedia applications makes it a complex balancing act. Our research indicates that a hybrid FD-SOI/Bulk, high-k/metal-gate platform is an excellent candidate for such applications, most probably around the 22nm node.
We have now demonstrated the successful integration of intellectual property (IP) for hybrid FD-SOI devices at 32nm using SOI wafers with extra-thin (ET) top silicon and ultra-thin (UT) box. Read More
IBM’s roadmap to ETSOI – Extremely Thin Silicon on Insulator – calls for very thin, very flat SOI substrates. Here’s why.
ETSOI transistors are thin-channel planar devices. Halo implantation is used to control electrostatics in conventional transistors. Although the halo controls the short channel effects, it also causes large random doping fluctuations and increases junction leakage and GILD, which are critical to low power platforms.
Electrostatics for ETSOI devices on the other hand, are controlled by the thin silicon on insulator (SOI) channel. One critical challenge is that threshold voltage variation for ETSOI is largely determined by silicon thickness variations. While ETSOI offers the promise of improved device characteristics, when billions or more of these transistors are integrated to create large scale circuits, the circuit performance will depend to a large extent on the flatness of the starting SOI wafer. Read More
Leti has compact models ready for FD-SOI SPICE simulations.
A critical link in the move to FD-SOI is the availability of robust compact models. Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing.
Extremely thin FD-SOI (ETSOI) technologies offer an excellent alternative to bulk thanks to great electrostatic control and low variability. Naturally, the transistors have different characteristics than current generations of bulk or partially depleted (PD) SOI, so new models are necessary. Read More
FD-SOI solves challenges without complicating design and manufacturing.
Designing a successful consumer-type IC requires a balanced combination of:
Figure 1 illustrates how just a few key features intrinsic to FD-SOI translate into advantages that serve those needs. Read More
FD-SOI is making the move towards industrialization. In this issue of ASN, experts from IBM, ST, Hitachi, Leti and Soitec detail their approaches.
In planar FD-SOI (as opposed to the verticality of FinFETs), CMOS transistors are built into an ultra-thin layer of silicon over a Buried Oxide (BOx) (which can optionally be extremely thin, too). This makes them Ultra-Thin Body Devices, with unique characteristics.
Planar FD-SOI addresses the major scaling challenges beyond the 28nm node:
As a result, the unique properties of fully depleted devices – combined with the simplicity of a planar FD-SOI process and optimized wafer costs – put FD-SOI in the cost-of-ownership “sweet spot” for finished chips. Read More
There’s no need to wait – Hitachi’s SOTB solution also benefits today’s mainstream low-power nodes.
Hitachi’s Hybrid Silicon-On-Thin-Box (SOTB)-Bulk technology offers many benefits for low-power system-on-chips (SOCs) at 45nm – and even at 65nm. There is no reason to wait for 22nm to start taking advantage of them.
The four most significant reasons to change to this solution now rather than later are that hybrid SOTB:
1. cuts power and leakage in half
2. gets threshold voltage (Vt) and variability under control
3. is fully compatible with current bulk design is easy to manufacture.
4. is easy to manufacture. Read More
Leading equipment and materials suppliers have created the European 450mm Equipment and Materials Initiative – or EEMI 450, for short. The steering committee comprises two substrate manufacturers (Soitec and Siltronic), three equipment suppliers (ASML, ASM, Recif), academics (IMEC, FHG) and Intel.
The initiative has recently been approved as an ENIAC program, making it eligible for research funding on a European level. This project marks the first time that all the major European equipment and materials suppliers, leading research institutes and related partners – a total of 28 at this time – have engaged in such broad cooperation.
The initiative is also designated as a SEMI Special Interest Group (SIG).
A task group within the initiative is dedicated to 450mm SOI proof-of-concept. Soitec will demonstrate 450mm SOI wafers, and has indicted that they will be ready to meet the initiative’s R&D and testbed needs.
Key advances in transistor research start on SOI.
SOI has always been the substrate of choice to explore new silicon device concepts and structures. The full dielectric isolation of the silicon allows one to dismiss the sometimes complex junction isolation schemes used in bulk silicon. The possibility of making devices in thin silicon films has enabled a number of new operation modes such as: volume inversion, where the bulk of the silicon film is inverted; and accumulation-mode operation, in which the channel region has the same doping polarity as the source and drain.
It is only afterwards that bulk processes are devised to mimic the original SOI device: the bulk FinFET is a bulk silicon version of the DELTA device or the SOI FinFET; and the double-gate silicon-on-nothing device is a version of the gate-all-around FET that does not use SOI wafers.
Another key advantage of SOI is the possibility of fully depleting a device. This is obviously not possible in bulk silicon.
Fully depleted MOSFETs have long been known to be “ideal” transistors, featuring optimal subthreshold slope, optimal body effect, better current drive, transconductance and linearity than bulk transistors, and lower soft error rate. They also show lower leakage currents and threshold voltage variation when temperature is increased.
Yet, these devices have not yet been widely adopted by industry. Recent findings by Leti and other research groups show that transistor parameter variability can be reduced when using FD-SOI. This may be the trigger point that may convince the industry.
We can add to the picture the fact that “remote” or “virtual” doping can be achieved using the “back-gate mirror doping” technique, in which forming a doping profile in the substrate below a thin BOX is found to “induce” a similar doping profile in the thin-film SOI device above the BOX. This effect can be used to modulate the virtual doping concentration in channels that are, otherwise, lightly doped or undoped.
But there are also very exciting results at the other side of the doping concentration scale. The recently published junctionless transistor is a heavily doped silicon SOI nanowire pi-gate FET with no junctions nor doping concentration gradients. The doping concentration is as high as what is normally used in source and drain.
Interestingly, the use of very high doping concentrations eliminates the problem of doping fluctuations just as well as the use of undoped channels does. Having no junctions is an obvious advantage when you are considering sub-22nm nodes. It also greatly facilitates the use of semiconductor materials other than silicon.
After having worked on SOI devices for the better part of the last 30 years, I still find it is a fascinating field of research, especially if one considers the advent of quantum effects in nanoscale SOI devices.
 “Back-gate Mirror Doping for Fully Depleted Planar SOI Transistors with Thin Buried Oxide”, R. Yan et al., 2010 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), April 2010
 “Nanowire transistors without junctions”, J-P Colinge, et al., Nature Nanotechnology, Vol. 5, No. 3, pp. 225-229, 2010