Tag Archive bonding

MIT-Singapore Alliance Get EVG Bonder

EVG850LTlores

Equipment maker EVG announced that the Singapore-MIT Alliance for Research Technology (SMART) ordered an EVG®850LT fully automated production bonding system designed for SOI and direct wafer bonding using low-temp plasma activation processing (press release here). SMART researchers will use the system to support  advanced substrate development efforts.  According to Professor Eugene Fitzgerald from MIT’s Department of Materials Science and Engineering, SMART chose the EVG850LT for the center’s advanced R&D efforts due to the system’s high process flexibility and performance, EVG’s experience in low-temperature bonding, and expertise and support in process development.

Peregrine Ships 2 Billionth UltraCMOS Chip, Signs with GlobalFoundries, Celebrates 25 Years of RF-SOI

Peregrine Semi's new UltraCMOS 10 RF-SOI technology platform gives smartphone manufacturers unparalleled flexibility and value without compromising quality for devices ranging from 3G through LTE networks.(Photo: Business Wire)

Peregrine Semi’s new UltraCMOS 10 RF-SOI technology platform gives smartphone manufacturers unparalleled flexibility and value without compromising quality for devices ranging from 3G through LTE networks. (Photo: Business Wire)

Peregrine Semiconductor announced that it has shipped its 2 billionth chip, released version 10 of its UltraCMOS RF-SOI technology, and is working with GlobalFoundries.

UltraCMOS technology is an advanced RF-SOI process, the latest versions of which leverage bonded silicon-on-sapphire (BSOS) substrates from Soitec. Peregrine did an excellent article for ASN last spring, clearly explaining the use of sapphire as a highly insulating substrate for RF-SOI CMOS processing.

IP Value Starts at the Substrate Level

If you say “IP” in the chip business, everyone thinks of cores and design. But in fact, the importance of intellectual property for chips can extend right down to the substrate level.

Engineered, advanced wafer substrates open new doors for designers. For example, Soitec recently announcement that we are licensing some of our Smart Stacking™ generic bonding IP related to back-side illumination (BSI)  in image sensors to TSMC. This is a clear testament to the value of IP starting at the substrate level. But in fact, TSMC is not the first company licensing our portfolio for BSI: ST took a license for BSI a few years ago.

Soitec is known throughout the industry for our Smart CutTM technology, the enabler of the silicon-on-insulator (SOI) wafer revolution. Most of today’s industry-leading SOI wafers destined for chip manufacturing are made by wafer suppliers using the Smart Cut layer transfer technology. The Smart Cut technology is also behind the development of new families of standard and custom engineered wafers.

In fact, Soitec’s IP portfolio extends to over 3000 patents covering over 600 inventions, and every year, we add about 350 more patents.  This gives us what is arguably the most complete advanced substrate engineering portfolio in the world.

smart-stacking

So when speaking of Soitec’s expertise, we might think first of SOI wafers, but in fact, such IP is generic. It can be used as building blocks in leading-edge microelectronic products, applied to an array of materials covering a wide realm of applications.

For example, Smart Cut™ technology is now being leveraged by Sumitomo Electric to produce GaN substrates for high-performance LED lighting applications. Following the announcement of last year, Sumitomo is now industrializing the product and investing in Smart Cut technology.

In the case of Soitec’s Smart Stacking™ generic bonding technology, one of the earliest applications was indeed BSI image sensors, to help manufacturers to deliver increased sensitivity and smaller pixel size. But Smart Stacking will also be leveraged to dramatically improve the performance of RF products, opening new doors to future RF and 3D-integration applications.

One example of how effective our IP policy is came about in 1997 when we contracted with  Shin-Etsu Handotai Co., Ltd (SEH) of Japan for SOI manufacturing using our Smart Cut technology. The manufacturing agreement helped establish SOI products made with Smart Cut technology as the global standard.

Last year, Soitec and SEH (which is the world leader in the manufacturing of silicon wafers) announced a Smart Cut™ licensing extension and expanded technology cooperation agreement. The new partnership includes an extended 10-year licensing agreement between the two companies and establishes a new level of joint technology cooperation. It will facilitate the development and wafer supply of SOI wafers to meet major market opportunities such as SOI for RF devices, FinFETs on SOI and FD-SOI.

The agreement expands the scope of the partnership between Soitec and SEH, including cross-licensing Smart Cut related patents between the two companies. SEH will now also be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), thereby further expanding the scope of applications.

Soitec’s expertise also extends to the domain of III-V epitaxy, which is leveraged in substrates for applications like RF, power, and lighting.

Beyond microelectronics, we are leveraging and expanding our innovation portfolio in energy markets. For example, earlier this year we announced the industry’s first four-junction solar cell for concentrator photovoltaic systems. We leverage both our proprietary semiconductor-bonding (Smart Stacking™) and layer-transfer (Smart Cut™) technologies to successfully stack non-lattice-matched materials while also raising the possibility of re-using expensive materials. These cells have recently reached efficiency of 44.7%, setting the world record.

The Soitec IP portfolio now represents over 20 years of successful innovation at the substrate level.   We invest around 10% of our revenue in R&D to develop and perfect breakthrough materials technologies. Our R&D teams work closely with manufacturers, as well as with laboratories such as CEA-Leti and the Fraunhofer Institute for Solar Energy Systems. We also take full advantage of the high-tech resources available in and around all of our locations worldwide.

In short, the innovations found in our substrate engineering IP portfolio are at the heart of how we lead, grow and maximize value through incremental and breakthrough solutions for the electronics and energy industries.

III-V wafer bonding has enabled a new world record for the conversion of sunlight into electricity, announced the Fraunhofer Institute for Solar Energy Systems ISE, Soitec, CEA-Leti and the Helmholtz Center Berlin.

Solar Cell

World record solar cell with 44.7% efficiency, made up of four solar subcells based on III-V compound semiconductors for use in concentrator photovoltaics. (Photo ©Fraunhofer ISE)

III-V wafer bonding has enabled a new world record for the conversion of sunlight into electricity, announced the Fraunhofer Institute for Solar Energy Systems ISE, Soitec, CEA-Leti and the Helmholtz Center Berlin. Creating a new solar cell structure with four solar subcells, the team took the lead after only over three years of research, entering the roadmap with a new record efficiency of 44.7%. This indicates that 44.7% of the solar spectrum’s energy, from ultraviolet through to the infrared, is converted into electrical energy. This is a major step towards reducing further the costs of solar electricity and continues to pave the way to the 50% efficiency roadmap. Wafer bonding plays a central role, as it enables the connection of two semiconductor crystals that otherwise cannot be grown on top of each other with high crystal quality. This produces the optimal semiconductor combination for the highest efficiency solar cells.

A few weeks prior, Soitec announced the launched of a new solar-energy concentrated photovoltaic (CPV) module featuring 31.8% efficiency, the highest of any commercial module being mass produced today.

Peregrine Semi’s RF Chip On Bonded SOS Is Main Antenna Switch in Samsung Galaxy S4 LTE-A – That’s SOI!

Peregrine has announced that the company’s new UltraCMOS antenna switch is driving RF performance in the Samsung Galaxy S4 LTE-A smartphone.

UltraCMOS technology is an advanced RF SOI process leveraging bonded silicon-on-sapphire (BSOS) substrates from Soitec. The new dual SP7T Multiswitch in the Samsung leverages Peregrine’s latest version of its UltraCMOS® process technology, STeP8 for RF Front End ICs.

The PE421280 MultiSwitch solves complex carrier aggregation challenges, says Peregrine. Samsung chose it for its ability to support simultaneous multi-band operation of up to 14 frequency bands while delivering exceptional linearity, insertion loss performance and small size.

Samsung Galaxy S4 LTE-A

With Peregrine Semi’s main antenna switch on BSOS substrates from Soitec, the Samsung Galaxy S4 LTE-A smartphone can support 14 frequency bands simultaneously, for a three-fold improvement in download times.
(Image courtesy Samsung)

The Samsung Galaxy S4 marks the first implementation on the 4G LTE-A network. The LTE-A protocol uses carrier aggregation – or the simultaneous reception of multiple frequency bands – to improve data throughput. According to Samsung, a three-minute download over 4G LTE would only take about one minute on 4G LTE-A.

“The data throughput enabled by LTE-A dramatically improves the wireless experience, and we are pleased to support a leader like Samsung in delivering this technology to consumers,” said Jim Cable, CEO of Peregrine Semiconductor. “Peregrine’s MultiSwitch devices are designed specifically to solve the challenges of carrier aggregation as used in LTE-A platforms. Based on our UltraCMOS technology, the devices feature not only the linearity required for simultaneous, multi-band switching performance, but also the integration, low power, and manufacturability required of high-volume consumer applications.”

UltraCMOS

(Image courtesy Peregrine Semiconductor)

High linearity and isolation performance are critical to ensure that radio signals don’t spill into other bands during multi-band operation.

As you may have seen in the ASN Buzz in recent months, this announcement about the Samsung phone is latest in a steady stream of product announcements and design wins (others include LG and Pantech) from Peregrine leveraging the latest UltraCMOS technology.

Just announced this week is the PE42423 RF Switch, which the company says is the highest isolation, carrier-grade Wi-Fi switch, delivering delivers 50 times more isolation and 10 times better linearity for 802.11ac Wi-Fi access points.

If you’d like to understand more of the technology details, Peregrine did an excellent article for ASN last spring, clearly explaining the use of sapphire as a highly insulating substrate for RF SOI CMOS processing. As stated there, “Peregrine Semiconductor’s UltraCMOS technology involves combining silicon with the highly-insulating substrate without incurring major defects, resulting in a highly-manufacturable semiconductor process. This process can be implemented in any standard CMOS foundry, leveraging existing CMOS capacity and avoiding substantial investment.”

UltraCMOS

The UltraCMOS process, an advanced form of RF SOI technology, can be implemented in any standard CMOS foundry.
(Image courtesy Peregrine Semiconductor)

The article concludes, “STeP10 devices are currently in laboratory evaluation and the results look promising to follow this path, with no foreseen limits to advancing the technology further. ”

That’s SOI in action!