Synopsys has announced a comprehensive RTL-to-GDSII solution for GlobalFoundries 22nm technology process. The implementation and signoff tools from the Synopsys Galaxy™ Design Platform have been enabled for the current version of GF’s’ 22FDX™ platform reference flow. GF has qualified these tools to use body bias to manage power, performance and leakage to achieve optimal energy efficiency and cost effectiveness. (See the press release here.)
The Galaxy Design Platform supports body biasing techniques throughout the design flow, key to achieving optimal power and performance when using the 22FDX technology. Both forward body bias and reverse body bias are supported, enabling power/performance trade-offs to be made dynamically and delivering up to 50% power reduction.
The reference flow using the Galaxy Design Platform is now available for early customer engagement.
ATopTech, a leader in next-generation physical design solutions, has announced that their Aprisa™ and Apogee™ Place & Route tools are now enabled for the current version of the GlobalFoundries 22FDX™ platform reference flow. GF has qualified these tools for the 22FDX reference flow to provide customers with the design flexibility of using body bias to manage power, performance and leakage needed to create the next-generation chips for mainstream mobile, IoT and networking applications. (Read the press release here.)
ATopTech tools provide designers with the capability to intelligently and dynamically tune the power and performance of the next-generation system-on-chip (SoC) designs.
The recent LetiDays FD-SOI workshop in Grenoble was the biggest show of force to date for the burgeoning FD-SOI ecosystem. In addition to a raft of excellent presentations, we learned two very big pieces of news. First, GlobalFoundries provided more insights into their upcoming FD-SOI offering. And second, designers opting for Samsung’s 28nm FD-SOI offering can get all their IP (with Samsung numbering) directly from (and supported by) Synopsys.
In fact the workshop marked the first time that the entire ecosystem took to the same stage. It was great. Here’s a recap.
Although not “officially” announced yet, GlobalFoundries was there to talk about their FD-SOI offering. In his presentation on Design/Technology Opimizations for FD-SOI, Gerde Teepe, Design Enablement Director at GF in Dresden, said theirs would be 22nm FD-SOI. That translates to a 14nm front-end with two double-patterning layers, and 28nm upper interconnect layers in the back-end. Currently working on body-biasing generators, they’re on target to be completely ready for business by the end of the year (see slide below).
The decision to go with a 14nm front-end was customer driven, said Dr. Teepe. They wanted a shrink, but they didn’t want to drive up the cost, hence the 28nm back-end.
The conference made clear that there’s no more “chicken-egg” IP problem for FD-SOI. IP is ready, and everyone wants to talk about it.
Kelvin Low, Senior Director of Foundry Marketing at Samsung said they’re driving 28nm FD-SOI to get “massive support” for the ecosystem. It’s positioned as cost-effective, low-power solution for a long-lived node, he said, and yes, they’re getting new customers. Wafer level reliability tests were successfully completed last September, and product level reliability tests finished up in March.
This set the stage for the big IP news from Synopsys. Senior Director Mike McAweeney said that Synopsys is supplying both ST’s IP plus their own Synopsys IP to Samsung customers, with Samsung part numbers and Synopsys support.
IP is hot at Cadence, too, said Amir Bar-Niv, Senior Group Director for Design IP Marketing. Since February they’ve doubled the number of available IP to meet customer demand.
Proof of rising demand also came from CMP, which organizes multi-project wafer runs for 28nm FD-SOI. Over 191 customers in 32 countries have requested the PDK. (Click here to learn more about the service.)
New approaches to body biasing were mentioned in a number of presentations, including talks by ST, GF and Leti. GF’s working on their body-biasing generator for 22nm. ST’s got a new-generation compact body bias generator especially for IoT. And ST and Leti are working on a new generation of “adaptive” body biasing, adding another 30% in power savings.
In a very interesting keynote, Professor Boris Thurmann of Stanford looked at mixed-signal IC design. We’re about to fuse the physical and virtual worlds, he said, in a third paradigm: IoT. He cited lots of advantages of FD-SOI in meeting the ultra-low-power and RF challenges faced by analog designers.
FD-SOI attacks variability with tighter process corners and less random mismatch than competing processes. It enables “…a simpler design process, shorter design cycles, improved yield or improved performance at given yield”. You get outstanding switch performance (see slide) and better ways of dealing with junction capacitance.
FD-SOI renders a shift in RF to translational circuits (no inductors) more practical. It also enables smaller but higher performance digital blocks in apps for things like object recognition – and the list goes on.
Naim Ben-Hmida, Senior Manager of Mixed-Signal Design & Test at Ciena (they used to be Nortel), talked about optical transceivers in 28nm FD-SOI. We’re heading towards terabyte modems connecting cities, he said, putting enormous pressure on short-reach optical networks. Their 100Gb/s metro-regional transceiver integrates what was two ASICs and an FPGA into a single 28nm FD-SOI transceiver ASIC. In addition to power and performance, FD-SOI was the right solution for both time-to-market and cost, he said.
In closing, let’s swing back to the conference opening keynote by Thomas Skotnicki, ST’s FD-SOI godfather (you can also read his 2011 ASN piece on FD-SOI here). The key to the FD-SOI success story, he reminded us, is the thin buried oxide. That’s been the essence of his work for the last 26 years.
“You must believe in what you’re doing,” he said. Proof of his perseverence: his breakthrough paper was twice rejected by the IEEE in 1999 – but once they accepted it in 2000, they named it best paper of the year.
He gave a big thank you to Soitec for breakthroughs in SOI wafer manufacturing – the ultra-thin silicon and ultra-thin insulating BoX combination were the enabling tour-de-force.
Skotnicki added that for 14nm Soitec has taken the wafers to new heights. “At 14nm, we are very robust,” he concluded, noting that the Leti/ST VLSI Symposium 2015 (O. Faynot et al) paper showed 14nm FD-SOI matching or beating 14nm FinFET performance at low voltages. The future is wide open. FD-SOI, he says can go down to 5nm (compared to 3nm for FinFET).
And clearly, he’s a man who knows the future.
CEA-Leti, a leading global center for applied research in microelectronics, nanotechnologies and integrated systems, is proudly hosting its 17th LetiDays in Grenoble on June 24–25, 2015, and associated seminars and workshops on June 22nd, 23rd and 26th (click here to go to the registration site).
On June 22-23, Leti will present their first workshop on FD-SOI. This Forum brings together a stellar line-up from academia, semiconductor companies, system design houses and the EDA industry to build a vision of the strategic directions and state-of-the-art in FDSOI IC design. Click here to see the schedule – it’s impressive.
The big themes for this year’s Leti Days are Internet of Things-augmented mobility, and managing connected devices and the services and apps they offer. This also gives Leti a chance to show off their remarkable array of technological breakthroughs in silicon technologies, sensors, telecommunications, power management in wearable systems, health applications, the transport market up to the factory and cities of the future.
The event will feature 40+ conferences, many networking opportunities, a showroom and exhibition halls. You’ll hear and meet market leaders, startups, analysts and Leti technology experts. As with every Leti Days event, you’ll get a comprehensive vision of the latest innovations in key technologies and markets, and be provided with opportunities to complement your roadmaps with Leti expertise.
If you can’t make it to Grenoble, watch for other Leti Days coming up in San Francisco during Semicon West and in Tokyo, among others.
Is FD-SOI a better choice than FinFETs for my chip? In some high-profile forums, designers are now asking that question. And the result is coming back: almost certainly.
Is there a place for FinFETs? Of course there is. If it’s a really big digital chip – no significant analog integration, where leakage not your biggest concern because what you’re really after is the ultimate in performance, when you’ve got a mega-budget and you’re going to run in extremely high volume, absolutely, you can make a strong business case for bulk FinFETs.
But is that really where most designs are?
If you need high-performance but you have to consider leakage (think battery life), if you’ve got to integrate the real world (aka analog – think IoT), if your chip is not a monster in size and will run in high volume but you don’t have an unlimited budget, you should be looking hard at FD-SOI. That’s what the experts at the recent EDPS conference in Monterey, CA said, that’s what they’re starting to tell the press, and that’s what they’re saying here on ASN.
Combined with the pretty dazzling results of the first 28nm FD-SOI silicon from cryptocurrency chipmaker SFARDS (read about it here) and the promise of very-high volume FD-SOI chips hitting the shelves in 2016, it’s a whole new ballgame.
Richard Goering over at the Cadence and Herb Reiter writing for 3DInCites wrote excellent blogs covering the EDPS conference in Monterey, CA a few weeks ago. EDPS – for Electronic Design Process Symposium – is a small but influential conference for the EDA community. Session 1 was entitled “FinFET vs. FD-SOI – which is the Right One for Your Design?”, and it lasted the entire morning.
The session kicked off with a presentation by Tom Dillinger, CAD Technology Manager at Oracle. Richard covered this in-depth in Part 1 of his two-part write-up (read the whole thing here). Tom gave an overview of the two technologies, putting a big emphasis on the importance or working closely with your foundry whichever way you go.
And then came the panel discussion with questions from the audience, which Herb in his write-up (read it here) described as “heated”. Acknowledging that FinFET has the stronger eco-system, Herb noted that, “…when using FinFETs, designers complain about the modeling- and design complexities of fins, the need for double pattering (coloring), the higher mask cost and added variability the extra masking step introduces. If 10nm FinFETs will demand triple or even quadruple patterning, they may face a significant disadvantage, compared to the 14nm FD-SOI technology, currently in development.”
In Part 2 of his coverage (read it here), Richard highlighted some of the big questions put to the panelists:
The two foundry guys were very much of the opinion that FinFET and FD-SOI can and will co-exist. Jamie Schaeffer’s comment, as noted by Richard, really sums it up nicely: “For some applications that have a large die with a large amount of digital integration, and require the ultimate in performance, FinFET is absolutely the right solution. For other applications that are in more cost-sensitive markets, and that have a smaller die and more analog integration, FD-SOI is the right solution.”
There you have it!
Shaeffer was also very bullish on next-gen FD-SOI, noting that performance will climb by 40% with half as many immersion lithography layers as FinFETs. He also said that next-gen FD-SOI is 30% faster than 20nm HK/MG.
Marco Brambilla noted that for Synapse, the FD-SOI choice was all about leakage, especially in IoT products where you need a burst of activity and then absolute quiet in sleep mode. (They’re working on a 28nm FD-SOI chip that will go into very high-volume production in early 2016, Synapse Design recently told ASN – read about that here).
Boris Murmann said that extrinsic capacitance in FinFETS is “a mess”, which is “a nightmare” for the analog guys. “ It’s a beautiful transistor [FinFET] but I can’t use it.” Yes, Richard reported, that’s what the man said.
So indeed, there is a choice. And with FD-SOI, the experts are seeing that it’s a real one.
CEA-Leti’s newest version of its advanced compact model for FD-SOI is now available in all major SPICE simulators (get the press release here). The Leti-UTSOI2.1 is the latest version of Leti’s compact model for FD-SOI, which was first released in 2013. (Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing. )
Leti-UTSOI2.1 further improves predictability and accuracy. These improvements include a direct and predictive link between bi-dimensional device electrostatics and process parameters, a refined description of narrow-channel effects, improved accuracy of moderate inversion regime and gate tunneling current modeling.
“This new version of the ultra-thin SOI model, which affirms Leti’s continuing leadership in FD-SOI technology, is ideal for designers seeking differentiation in energy management and performance for advanced nodes,” said Leti CEO Marie-Noëlle Semeria
Leti-UTSOI2.1, which considerably extends the domain of physical device description compared to other solutions, is now available in most of the commercial SPICE and Fast SPICE simulators used by industry.
“ST needed a fast, practical method to ensure our IP would not be susceptible to noise issues, when implemented in complex, multi-million gate SoCs. We have also found we can optimize the power-supply requirements to IP in the knowledge that both the position and number of pins or bumps will be adequate for the IP as implemented,” said Pierre Dautriche, Physical IP & Mixed Design Solutions Director, Central CAD & Design Solutions, STMicroelectronics. “Extensive use here has proven WaveIntegrity as the most efficient and effective way to achieve these aims, allowing us to reduce risk in ways previously impossible. This capability is being extended to both our most advanced and older process nodes, and which we will also support for our own customers. ”
ST is using WaveIntegrity across groups designing complex IP for home and automotive devices. Getting a fast, initial picture of potential noise-related issues is vital in designing today’s complex SOCs and WaveIntegrity performs noise-analysis results right from the initial floorplan, as IP is delivered to the chip assembly team.
WaveIntegrity encourages noise-analysis results to be used during the first and subsequent floorplan stages, so that critical design decisions can be made early and at low cost. The analysis setup is then refined for the final floorplan revision to support any potential remaining noise-related design choices before final place & route.
Some years back, European research giant CEA-Leti made a major commitment to support FD-SOI, partnering with STMicroelectronics, Soitec and IBM. Now, with the big FD-SOI foundry announcement by Samsung and STMicroelectronics, Leti’s ready to bring its vast expertise to players throughout the value chain, right up through design integration.
To learn more about the range Leti covers, you may also want to check out the “Leti Day” conferences around the world, where they showcase their technology. The next one is in Grenoble (24-26 June, registration site here), followed by an invitation-only event during Semicon West (info here), as well as events in Paris and Tokyo.
ASN recently caught up again with Laurent Malier, CEO of CEA-Leti to get his take on the ST-Samsung news. (A few months ago, we did an in-depth interview with Malier on the massive role Leti plays in the FD-SOI ecosystem — click here to read it if you missed it then).
Here are some excerpts from our conversation.
Advanced Substrate News (ASN): What does the Samsung-ST announcement mean for Leti?
Laurent Malier (LM): It means the success of our strategy. For years, we’ve been heavily investing in FD-SOI technology, committing critical scientific and technological support at each phase of FD-SOI development. We were very confident that it was the best option for balancing performance, energy efficiency and cost. In terms of technology and performance, that was very clearly demonstrated last year at CES and in Barcelona. In addition to performance you need to go into manufacturing, secure the ramp-up, secure the costs, and secure the full ecosystem. We worked very hard on all these things over the last year and a half. But the last brick was missing: securing a foundry for the second source and enlarging access to the technology. Now we have it: the ST-Samsung announcement gives us the opportunity to showcase our work and our methodology
ASN: In which areas did Leti contribute to FD-SOI development?
LM: Leti really took a global approach in the development of FD-SOI. Of course, the SOI substrate is based on a Leti invention. Device research was done by Leti teams with our ecosystem of partners at three different sites, first in Grenoble, and later at Crolles [ST] and Albany [IBM]. We were also active in the modeling (UTSOI models implemented in all EDA tools were developed by Leti) and design kit development, so that a complete design kit was available for designers. We had designers who worked for several years in order to prove the results at the circuit level. And we have several customers for whom we’re deploying the technology in their applications. So from raw material to architecture and application design, we have a global footprint.
Because FD-SOI is an enabling technology, we need to do more than support the “push” – we also need to support the “pull” in exploring applications that will benefit from this technology. This is something else we do. Leti is not only a silicon technology institute but also is focused on applications. Half of our activity looks at application opportunities – especially for telecom, IoT, healthcare, automotives and power management.
ASN: Do you see opportunities for FD-SOI in IoT?
LM: For me, the first wave of IoT will be in machine-to-machine [M2M] and process monitoring, so that’s synergistic with sensors. Because your objects are connected, you’ll greatly expand your ability to explore data. You’ll need more efficient local data processing and more efficient data transmission – so these are places for FD-SOI circuits. For companies that are interested in any part of the value chain – design, sensor integration and so forth – these are areas where we are leaders and can provide expertise. Look for more announcements coming up at Leti Days.