Tag Archive EDA

ByGianni PRATA

Synopsys RTL-to-GDSII solution qualified for GF’s 22nm FD-SOI (including body biasing)

Synopsys has announced a comprehensive RTL-to-GDSII solution for GlobalFoundries 22nm technology process. The implementation and signoff tools from the Synopsys Galaxy™ Design Platform have been enabled for the current version of GF’s’ 22FDX™ platform reference flow. GF has qualified these tools to use body bias to manage power, performance and leakage to achieve optimal energy efficiency and cost effectiveness. (See the press release here.)

The Galaxy Design Platform supports body biasing techniques throughout the design flow, key to achieving optimal power and performance when using the 22FDX technology. Both forward body bias and reverse body bias are supported, enabling power/performance trade-offs to be made dynamically and delivering up to 50% power reduction.

The reference flow using the Galaxy Design Platform is now available for early customer engagement.

ByGianni PRATA

Leading SOC Place-and-Route Tools Qualified for GF’s 22FDX; includes dynamic tuning

ATopTech, a leader in next-generation physical design solutions, has announced that their Aprisa™ and Apogee™ Place & Route tools are now enabled for the current version of the GlobalFoundries 22FDX™ platform reference flow. GF has qualified these tools for the 22FDX reference flow to provide customers with the design flexibility of using body bias to manage power, performance and leakage needed to create the next-generation chips for mainstream mobile, IoT and networking applications. (Read the press release here.)

ATopTech tools provide designers with the capability to intelligently and dynamically tune the power and performance of the next-generation system-on-chip (SoC) designs.

ByAdministrator

Yes! FD-SOI IP Ready for GF, Samsung; Ecosystem Now a Force to Be Reckoned With

The recent LetiDays FD-SOI workshop in Grenoble was the biggest show of force to date for the burgeoning FD-SOI ecosystem. In addition to a raft of excellent presentations, we learned two very big pieces of news. First, GlobalFoundries provided more insights into their upcoming FD-SOI offering. And second, designers opting for Samsung’s 28nm FD-SOI offering can get all their IP (with Samsung numbering) directly from (and supported by) Synopsys.

In fact the workshop marked the first time that the entire ecosystem took to the same stage. It was great. Here’s a recap.

GF: 22 = 14 + 28

GF_FDSOIenablement_LetiDays15

(Courtesy: GlobalFoundries)

Although not “officially” announced yet, GlobalFoundries was there to talk about their FD-SOI offering. In his presentation on Design/Technology Opimizations for FD-SOI, Gerde Teepe, Design Enablement Director at GF in Dresden, said theirs would be 22nm FD-SOI. That translates to a 14nm front-end with two double-patterning layers, and 28nm upper interconnect layers in the back-end. Currently working on body-biasing generators, they’re on target to be completely ready for business by the end of the year (see slide below).

GF_FDSOI_LetiDays15_phases

Most of the challenges for delivering their 22nm FD-SOI offering have been met, said Gerde Teepe, Design Engineering Director at GF/Dresden.The final phase will be completed by the end of this year. (FD-SOI Workshop, LetiDays 2015)

The decision to go with a 14nm front-end was customer driven, said Dr. Teepe. They wanted a shrink, but they didn’t want to drive up the cost, hence the 28nm back-end.

IP, IP, IP

The conference made clear that there’s no more “chicken-egg” IP problem for FD-SOI. IP is ready, and everyone wants to talk about it.

Samsung_FDSOI_design_LetiDays15

(Courtesy: Samsung)

Kelvin Low, Senior Director of Foundry Marketing at Samsung said they’re driving 28nm FD-SOI to get “massive support” for the ecosystem. It’s positioned as cost-effective, low-power solution for a long-lived node, he said, and yes, they’re getting new customers. Wafer level reliability tests were successfully completed last September, and product level reliability tests finished up in March.

Synopsys_FDSOI_IP_LetiDays15

Synopsys Senior Director Mike McAweeney explaining their Samsung IP strategy at the LetiDays ’15 FD-SOI Workshop.

This set the stage for the big IP news from Synopsys. Senior Director Mike McAweeney said that Synopsys is supplying both ST’s IP plus their own Synopsys IP to Samsung customers, with Samsung part numbers and Synopsys support.

IP is hot at Cadence, too, said Amir Bar-Niv, Senior Group Director for Design IP Marketing. Since February they’ve doubled the number of available IP to meet customer demand.

Proof of rising demand also came from CMP, which organizes multi-project wafer runs for 28nm FD-SOI. Over 191 customers in 32 countries have requested the PDK. (Click here to learn more about the service.)

Body Biasing Goes Adaptive

New approaches to body biasing were mentioned in a number of presentations, including talks by ST, GF and Leti. GF’s working on their body-biasing generator for 22nm. ST’s got a new-generation compact body bias generator especially for IoT. And ST and Leti are working on a new generation of “adaptive” body biasing, adding another 30% in power savings.

Hot Topic: Analog

Thurmann_analogFDSOI_design_LetiDays15

FD-SOI advantages for analog design include outstanding switch performance, said Boris Thurmann of Stanford. (LetiDays ’15)

In a very interesting keynote, Professor Boris Thurmann of Stanford looked at mixed-signal IC design. We’re about to fuse the physical and virtual worlds, he said, in a third paradigm: IoT. He cited lots of advantages of FD-SOI in meeting the ultra-low-power and RF challenges faced by analog designers.

FD-SOI attacks variability with tighter process corners and less random mismatch than competing processes. It enables “…a simpler design process, shorter design cycles, improved yield or improved performance at given yield”. You get outstanding switch performance (see slide) and better ways of dealing with junction capacitance.

FD-SOI renders a shift in RF to translational circuits (no inductors) more practical. It also enables smaller but higher performance digital blocks in apps for things like object recognition – and the list goes on.

Naim Ben-Hmida, Senior Manager of Mixed-Signal Design & Test at Ciena (they used to be Nortel), talked about optical transceivers in 28nm FD-SOI. We’re heading towards terabyte modems connecting cities, he said, putting enormous pressure on short-reach optical networks. Their 100Gb/s metro-regional transceiver integrates what was two ASICs and an FPGA into a single 28nm FD-SOI transceiver ASIC. In addition to power and performance, FD-SOI was the right solution for both time-to-market and cost, he said.

You Gotta Believe

In closing, let’s swing back to the conference opening keynote by Thomas Skotnicki, ST’s FD-SOI godfather (you can also read his 2011 ASN piece on FD-SOI here). The key to the FD-SOI success story, he reminded us, is the thin buried oxide. That’s been the essence of his work for the last 26 years.

“You must believe in what you’re doing,” he said. Proof of his perseverence: his breakthrough paper was twice rejected by the IEEE in 1999 – but once they accepted it in 2000, they named it best paper of the year.

ST_Skotnicki_FDSOI_LetiDays15

(Courtesy: STMicroelectronics)

He gave a big thank you to Soitec for breakthroughs in SOI wafer manufacturing – the ultra-thin silicon and ultra-thin insulating BoX combination were the enabling tour-de-force.

Skotnicki added that for 14nm Soitec has taken the wafers to new heights. “At 14nm, we are very robust,” he concluded, noting that the Leti/ST VLSI Symposium 2015 (O. Faynot et al) paper showed 14nm FD-SOI matching or beating 14nm FinFET performance at low voltages. The future is wide open. FD-SOI, he says can go down to 5nm (compared to 3nm for FinFET).

And clearly, he’s a man who knows the future.

ByGianni PRATA

Don’t Miss Leti Days and FD-SOI Workshop (Grenoble, 22-26 June)

LetiDaysheader_registration_lowresCEA-Leti, a leading global center for applied research in microelectronics, nanotechnologies and integrated systems, is proudly hosting its 17th LetiDays in Grenoble on June 24–25, 2015, and associated seminars and workshops on June 22nd, 23rd and 26th (click here to go to the registration site).

On June 22-23, Leti will present their first workshop on FD-SOI. This Forum brings together a stellar line-up from academia, semiconductor companies, system design houses and the EDA industry to build a vision of the strategic directions and state-of-the-art in FDSOI IC design. Click here to see the schedule – it’s impressive.

The big themes for this year’s Leti Days are Internet of Things-augmented mobility, and managing connected devices and the services and apps they offer. This also gives Leti a chance to show off their remarkable array of technological breakthroughs in silicon technologies, sensors, telecommunications, power management in wearable systems, health applications, the transport market up to the factory and cities of the future.

The event will feature 40+ conferences, many networking opportunities, a showroom and exhibition halls. You’ll hear and meet market leaders, startups, analysts and Leti technology experts. As with every Leti Days event, you’ll get a comprehensive vision of the latest innovations in key technologies and markets, and be provided with opportunities to complement your roadmaps with Leti expertise.

If you can’t make it to Grenoble, watch for other Leti Days coming up in San Francisco during Semicon West and in Tokyo, among others.

ByAdministrator

FinFET or FD-SOI? Designers have a real choice, say experts

Is FD-SOI a better choice than FinFETs for my chip? In some high-profile forums, designers are now asking that question. And the result is coming back: almost certainly.

Is there a place for FinFETs? Of course there is. If it’s a really big digital chip –  no significant analog integration, where leakage not your biggest concern because what you’re really after is the ultimate in performance, when you’ve got a mega-budget and you’re going to run in extremely high volume, absolutely, you can make a strong business case for bulk FinFETs.

But is that really where most designs are?

Cannery Row at twilight

(Photo credit: Monterey County Convention and Visitors Bureau)

If you need high-performance but you have to consider leakage (think battery life), if you’ve got to integrate the real world (aka analog – think IoT), if your chip is not a monster in size and will run in high volume but you don’t have an unlimited budget, you should be looking hard at FD-SOI. That’s what the experts at the recent EDPS conference in Monterey, CA said, that’s what they’re starting to tell the press, and that’s what they’re saying here on ASN.

Combined with the pretty dazzling results of the first 28nm FD-SOI silicon from cryptocurrency chipmaker SFARDS (read about it here) and the promise of very-high volume FD-SOI chips hitting the shelves in 2016, it’s a whole new ballgame.

EDA experts weigh in at EDPS

Richard Goering over at the Cadence and Herb Reiter writing for 3DInCites wrote excellent blogs covering the EDPS conference in Monterey, CA a few weeks ago. EDPS – for Electronic Design Process Symposium – is a small but influential conference for the EDA community. Session 1 was entitled “FinFET vs. FD-SOI – which is the Right One for Your Design?”, and it lasted the entire morning.

EDPSlogoThe session kicked off with a presentation by Tom Dillinger, CAD Technology Manager at Oracle. Richard covered this in-depth in Part 1 of his two-part write-up (read the whole thing here). Tom gave an overview of the two technologies, putting a big emphasis on the importance or working closely with your foundry whichever way you go.

And then came the panel discussion with questions from the audience, which Herb in his write-up (read it here) described as “heated”. Acknowledging that FinFET has the stronger eco-system, Herb noted that, “…when using FinFETs, designers complain about the modeling- and design complexities of fins, the need for double pattering (coloring), the higher mask cost and added variability the extra masking step introduces. If 10nm FinFETs will demand triple or even quadruple patterning, they may face a significant disadvantage, compared to the 14nm FD-SOI technology, currently in development.”

EDPS_FF_FDSOI_panel

EDPS 2015 panelists debate FinFET vs. FD-SOI. (Left to right: Marco Brambilla (Synapse Design); Kelvin Low (Samsung); Boris Murmann (Stanford); Jamie Schaeffer (GlobalFoundries). (Image courtesy: Richard Goering and Cadence)

In Part 2 of his coverage (read it here), Richard highlighted some of the big questions put to the panelists:

  • Kelvin Low, Sr. Director Foundry Marketing for Samsung
  • Boris Murmann, Stanford professor and analog/mixed-signal expert
  • Marco Brambilla, Director of Engineering at Synapse Design
  • Jamie Schaeffer, Product Line Manager at GlobalFoundries

The two foundry guys were very much of the opinion that FinFET and FD-SOI can and will co-exist. Jamie Schaeffer’s comment, as noted by Richard, really sums it up nicely: “For some applications that have a large die with a large amount of digital integration, and require the ultimate in performance, FinFET is absolutely the right solution. For other applications that are in more cost-sensitive markets, and that have a smaller die and more analog integration, FD-SOI is the right solution.”

There you have it!

Shaeffer was also very bullish on next-gen FD-SOI, noting that performance will climb by 40% with half as many immersion lithography layers as FinFETs. He also said that next-gen FD-SOI is 30% faster than 20nm HK/MG.

Marco Brambilla noted that for Synapse, the FD-SOI choice was all about leakage, especially in IoT products where you need a burst of activity and then absolute quiet in sleep mode. (They’re working on a 28nm FD-SOI chip that will go into very high-volume production in early 2016, Synapse Design recently told ASN – read about that here).

Boris Murmann said that extrinsic capacitance in FinFETS is “a mess”, which is “a nightmare” for the analog guys. “ It’s a beautiful transistor [FinFET] but I can’t use it.” Yes, Richard reported, that’s what the man said.

So indeed, there is a choice. And with FD-SOI, the experts are seeing that it’s a real one.

 

ByGianni PRATA

Newest Leti Compact Model for FD-SOI Further Improves Predictability and Accuracy

TEM cross-section of FDSOI transistor (Courtesy of STMicroelectonics)

TEM cross-section of FDSOI transistor (Courtesy of STMicroelectonics)

CEA-Leti’s newest version of its advanced compact model for FD-SOI is now available in all major SPICE simulators (get the press release here). The Leti-UTSOI2.1 is the latest version of Leti’s compact model for FD-SOI, which was first released in 2013. (Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing. )

Leti-UTSOI2.1 further improves predictability and accuracy. These improvements include a direct and predictive link between bi-dimensional device electrostatics and process parameters, a refined description of narrow-channel effects, improved accuracy of moderate inversion regime and gate tunneling current modeling.

“This new version of the ultra-thin SOI model, which affirms Leti’s continuing leadership in FD-SOI technology, is ideal for designers seeking differentiation in energy management and performance for advanced nodes,” said Leti CEO Marie-Noëlle Semeria

Leti-UTSOI2.1, which considerably extends the domain of physical device description compared to other solutions, is now available in most of the commercial SPICE and Fast SPICE simulators used by industry.

ByAdministrator

Tokyo FD-SOI/RF-SOI Workshop (part 2): Sony 1mW FD-SOI GPS steals the show, but great presentations from EDA & design houses, too

The Sony presentation on a 28nm FD-SOI GPS chip for an IoT app, which cut power by 10x (down to 1mW), has gained enormous traction worldwide.  However, that was just one of a dozen excellent presentations made by industry leaders at the recent FD-SOI/RF-SOI workshop in Tokyo.

In part 1 of ASN’s coverage of the workshop (click here if you missed it), we took a quick look at the presentations by Samsung, ST, IBS, IBM and Lapis. Here in part 2, we’ll look at Sony’s, as well as the presentations from the big EDA vendors and the IP and design houses.

All of the presentations are now freely available on the SOI Consortium website (click here for the complete listing).

Low Power SOC design with RF circuit by the FD-SOI 28nm by Kenichi Nakano, Senior Manager, Section8 System Analog Product Department, Analog LSI Business Division, Device Solution Business Group, Sony Corporation

This presentation details Sony’s work on an 28nm FD-SOI version of its CXD5600GF Global Navigation Satellite System receiver LSI for smartphones and mobile products. When the bulk version was first released in 2013, the 10mW power consumption made it the industry’s lowest.  Now, with the 28nm FD-SOI version, they’ve gotten that down to a staggering 1mW – suitable for wearables. The presentation leads off by answering the question: Why FD-SOI? Sony engineers set themselves the challenge of a 0.6V target supply voltage for all logic, SRAM and analog (down from 1.1V in the previous generation). FD-SOI, especially leveraging body biasing, would enable them to attain this goal, providing a wide range of options for optimizing speed, power and area. The various steps and TEGs  (test element groups) are detailed in this presentation, and compared with 28nm and 40nm bulk. The advantages for low-power RF were particularly compelling.  This presentation has generated enormous attention in the press and in social media. For example, a week after EETimes published Sony Joins FD-SOI Club, it had been shared almost 200 times on LinkedIn.

Sony_Tokyo_FDSOI_GPS

(Courtesy: Sony)

 

Creation of high performance IP for FD-SOI by Kevin Yee, Director of Marketing, Cadence

As noted in this presentation, Cadence has existing solutions for 28nm FD-SOI, 14nm FD-SOI and 14nm FinFET-SOI. They have provided full design enablement for ST and Samsung processes. This presentation shows several examples of IP.

Cadence_Tokyo_FDSOI

(Courtesy: Cadence)

 

28nm FD-SOI Design/IP Infrastructure by Shirley Jin, Sr. Director of Engineering, VeriSilicon

Headquartered in Shanghai, Verisilicon provides Silicon as a Platform Services (SiPaaS), taping out 50 chips a year for leading customers at foundries worldwide. This presentation presents extensive, detailed 28nm FD-SOI benchmarking data for the ARM Cortex A7. VeriSilicon has an extensive IP portfolio in 28nm FD-SOI, working design flow and infrastructure to execute the designs.

Verisilicon_Tokyo_28FDSOI_ARMbenchmark

Designing with FD-SOI – Benefits and Challenges by Huzefa Cutlerywala, Sr. Dir. Technical Solutions, Open-Silicon

Open-Silicon is a leader in traditional ASIC solutions, derivative and platform SoCs, hardware and software design and production handoffs. They are a channel partner for ST’s FD-SOI in Japan, have pipe-clean design flows for FD-SOI, and are currently taping out an FD-SOI test chip for a customer. They see FD-SOI as ideal for consumer and networking/telecom/storage/compute applications. This presention lists what they see as the benefits (which are impressive) and challenges (which are fairly minor), and provides some details on GPU and DSP cores.

OpenSilicon_Tokyo_FDSOI_DSPcore

(Courtesy: Open-Silicon)

 

Ultra Low Power Memory Solutions for FD-SOI by Paul Wells, CEO, SureCore

SureCore develops ultra-low power embedded SRAM IP. Making the point that memory typically dominates SoC area and can consume 70% of the power, SureCore sees FD-SOI as an elegant solution. Working samples of their SRAM solution in ST’s 28nm FD-SOI were received in March 2014, showing a 50% dynamic power savings, and high performance at low operating voltage. Extensive comparisons are given in this presentation.

Surecore_Tokyo_FDSOI_SRAM

(Courtesy: SureCore)

 

Synopsys FD-SOI IP Solutions by Mike McAweeney, Sr. Director, IP Product Sales, Synopsys

This presentation gives quite a detailed rundown of the ST-Synopsys 28FD-SOI IP program. Synopsys licenses a comprehensive, silicon-validated 28nm FD-SOI IP portfolio to Samsung’s foundry customers and other manufacturing partners. FD-SOI customers contract with Synopsys for standard Synopsys IP titles, with Synopsys customer support, part numbers, documentation and standard views. Slides 7 and 8 detail the commonly used interface, analog and display IPs available through Synopsys.

(Courtesy: Synopsys)

(Courtesy: Synopsys)

 

~ ~ ~

The next FD-SOI/RF-SOI full-day workshop will be held in San Francisco at the Palace Hotel on Friday February 27th 2015, the same week as ISSCC. A broad range of technology and design leaders from across the industry such as Cadence, Ciena, GlobalFoundries, IBM, IMEC, Samsung, STMicroelectronics, Synopsys and VeriSilicon will present compelling solutions in FD-SOI and RF-SOI technologies, including competitive comparisons and product results. Registration is mandatory, free and open to everyone – click here to go to the registration page on the SOI Consortium website. (Lunch will be offered to all the attendees.)

 

ByGianni PRATA

ST Chooses WaveIntegrity from CWS for Early Noise Analysis in FD-SOI SOCs

STMicroelectronics has chosen WaveIntegrityTM from CWS for rapid and practical analysis of noise issues in complex FD-SOI SOCs (press release here).

“ST needed a fast, practical method to ensure our IP would not be susceptible to noise issues, when implemented in complex, multi-million gate SoCs. We have also found we can optimize the power-supply requirements to IP in the knowledge that both the position and number of pins or bumps will be adequate for the IP as implemented,” said Pierre Dautriche, Physical IP & Mixed Design Solutions Director, Central CAD & Design Solutions, STMicroelectronics. “Extensive use here has proven WaveIntegrity as the most efficient and effective way to achieve these aims, allowing us to reduce risk in ways previously impossible. This capability is being extended to both our most advanced and older process nodes, and which we will also support for our own customers. ”

ST is using WaveIntegrity across groups designing complex IP for home and automotive devices. Getting a fast, initial picture of potential noise-related issues is vital in designing today’s complex SOCs and WaveIntegrity performs noise-analysis results right from the initial floorplan, as IP is delivered to the chip assembly team.

WaveIntegrity encourages noise-analysis results to be used during the first and subsequent floorplan stages, so that critical design decisions can be made early and at low cost. The analysis setup is then refined for the final floorplan revision to support any potential remaining noise-related design choices before final place & route.

ByAdministrator

Interview: Leti CEO Malier on the FD-SOI Breakthrough; Leti Days in Grenoble (24-26 June) & Semicon West

Some years back, European research giant CEA-Leti made a major commitment to support FD-SOI, partnering with STMicroelectronics, Soitec and IBM.  Now, with the big FD-SOI foundry announcement by Samsung and STMicroelectronics, Leti’s ready to bring its vast expertise to players throughout the value chain, right up through design integration.

To learn more about the range Leti covers, you may also want to check out the “Leti Day” conferences around the world, where they showcase their technology. The next one is in Grenoble (24-26 June, registration site here), followed by an invitation-only event during Semicon West (info here), as well as events in Paris and Tokyo.

ASN recently caught up again with Laurent Malier, CEO of CEA-Leti to get his take on the ST-Samsung news.  (A few months ago, we did an in-depth interview with Malier on the massive role Leti plays in the FD-SOI ecosystem — click here to read it if you missed it then).

LaurentMalierLeti

Laurent Malier, CEO of CEA-Leti

Here are some excerpts from our conversation.

Advanced Substrate News (ASN): What does the Samsung-ST announcement mean for Leti?

Laurent Malier (LM): It means the success of our strategy. For years, we’ve been heavily investing in FD-SOI technology, committing critical scientific and technological support at each phase of FD-SOI development. We were very confident that it was the best option for balancing performance, energy efficiency and cost.  In terms of technology and performance, that was very clearly demonstrated last year at CES and in Barcelona. In addition to performance you need to go into manufacturing, secure the ramp-up, secure the costs, and secure the full ecosystem. We worked very hard on all these things over the last year and a half. But the last brick was missing: securing a foundry for the second source and enlarging access to the technology. Now we have it: the ST-Samsung announcement gives us the opportunity to showcase our work and our methodology

 

ASN: In which areas did Leti contribute to FD-SOI development?

LM:  Leti really took a global approach in the development of FD-SOI. Of course, the SOI substrate is based on a Leti invention.  Device research was done by Leti teams with our ecosystem of partners at three different sites, first in Grenoble, and later at Crolles [ST] and Albany [IBM]. We were also active in the modeling (UTSOI models implemented in all EDA tools were developed by Leti) and design kit development, so that a complete design kit was available for designers. We had designers who worked for several years in order to prove the results at the circuit level. And we have several customers for whom we’re deploying the technology in their applications. So from raw material to architecture and application design, we have a global footprint.

Because FD-SOI is an enabling technology, we need to do more than support the “push” – we also need to support the “pull” in exploring applications that will benefit from this technology. This is something else we do. Leti is not only a silicon technology institute but also is focused on applications. Half of our activity looks at application opportunities – especially for telecom, IoT, healthcare, automotives and power management.

 

ASN: Do you see opportunities for FD-SOI in IoT?

LM: For me, the first wave of IoT will be in machine-to-machine [M2M] and process monitoring, so that’s synergistic with sensors. Because your objects are connected, you’ll greatly expand your ability to explore data.  You’ll need more efficient local data processing and more efficient data transmission – so these are places for FD-SOI circuits. For companies that are interested in any part of the value chain – design, sensor integration and so forth – these are areas where we are leaders and can provide expertise.  Look for more announcements coming up at Leti Days.

LetiDays2014

ByAdministrator

Synopsys Design Flow Support for Samsung-ST 28nm FD-SOI (With More Details on What Designers Need to Know)

Following the big FD-SOI/EDA news, Synopsys has provided ASN with more details for designers.

Samsung_ST_logos             snps_logo

The Synopsys’ Galaxy Design Platform has been extended to support the Samsung-STMicroelectronics strategic agreement on 28nm FD-SOI (see press release here).

They’ve covered all the bases, so that designers going to Samsung’s foundry services for ST’s 28nm FD-SOI can hit the ground running. Samsung’s vice president of foundry marketing, Dr. Shawn Han, says, “28-nm FD-SOI is an ideal solution for customers looking for extra performance and power efficiency at the 28-nm node without having to migrate to 20-nm. Our close collaboration with Synopsys and ST will enable designers to reduce risk, accelerate time-to-market, minimize power and maximize performance to expand 28-nm FD-SOI adoption.”

Synopsys has collaborated closely with ST on FD-SOI for several years now – Galaxy is already successfully silicon-proven in several 28nm FD-SOI SoCs with multi-core processors, says the company. And just a few weeks ago, Synopsys announced that ST had standardized on Synopsys’ IC Compiler™ place-and-route solution for all its CPU and GPU implementations inside its Design Enablement and Services organization (see that press release here).

Synopsys says that the Galaxy Design Platform enables designers to take full advantage of FD-SOI’s low power and high performance. “Because the Galaxy Design Platform is silicon-proven on ST’s 28-nm FD-SOI process with multiple tapeouts of low power designs running in the gigahertz frequency range, customers can adopt this technology with confidence,” said Antun Domic, executive vice president and general manager, Design Group at Synopsys. “Combined with the Lynx Design System and DesignWare® IP, the Galaxy Design Platform enables engineers to derive maximum benefit from the FD-SOI process and our continued collaboration with ST and Samsung will ensure ease of adoption of FD-SOI for SoC design.”

The Galaxy Design Platform is a suite of design tools that work in an integrated way for design on both the digital and analog sides. It enables concurrent area, power and timing optimizations to enable engineers to optimize their designs for the ST 28nm FD-SOI process. Synopsys says the advanced design enablement features like the IC Compiler™ tool’s concurrent clock and data optimization, layer-aware optimization, physical datapath and comprehensive support for hierarchical and low-power design features can also be directly accessed by Lynx users for high-performance and low-power CPU and GPU design.

The Lynx Design System is an automation environment for chip designers. Lynx incorporates the full Galaxy Platform for both digital and analog implementation and for comprehensive design analysis. With technology portability and designer productivity as goals, the Galaxy flow in Lynx is architected technology independent. The accompanying technology plug-in structure enables design teams to quickly setup and implement on new technology nodes. Additionally, the automation architecture in Lynx enables the inclusion of third-party developed scripts and tools. Synopsys collaborates with the foundries to encapsulate technology-specific scripts and settings in the plug-in accelerating project setup and design time.

FD-SOI Specifics

Specifically for ST 28FDSOI, Synopsys collaborated with ST on the development of an ICC-Kit supporting UPF (Unified Power Format) and back-bias connections. Synopsys also implemented and validated a Lynx technology plug-in, integrating technology specific settings and scripts from the ICC-Kit into Lynx. The resulting combination significantly reduces designer overhead and implementation time for SOI nodes like ST 28FDSOI. Designers still need to add constraints and optimizations for their specific design, including the UPF files that specify the power intent. IC Compiler will connect the well ties and voltage converters in a manner consistent with the power-intent specified in the UPF Files (using scripts from the ICC-Kit).

All this should enable broader market adoption of ST’s 28nm FD-SOI technology for SoC design. “The close collaboration between ST design teams and Synopsys led to advanced silicon-proven design enablement solutions that fully leverage the performance and power promise of FD-SOI technology and provide the foundation needed to meet tight time to market windows,” said Philippe Magarshack, executive vice president, Design Enablement and Services, STMicroelectronics.

So there’s no need to wait. The Synopsys Galaxy Design Platform and Lynx Design System with support for ST and Samsung 28-nm FD-SOI process technology are available now from Synopsys. The 28-nm FD-SOI-enabled PDK, standard cells and memories for early design are available now from Samsung.

There’s no more doubt about it: for FD-SOI, it’s full speed ahead!

Note: Many thanks to Synopsys for help on the technical details in this piece.

ARM TechCon video/tutorial — recommended viewing:

ST_ARMCon_FDSOI_slide39
If you’re a designer looking for a good overview, there’s an excellent ARM TechCon 2013 video on FD-SOI posted on the Synopsys site. David Jacquet from ST shares the company’s FD-SOI approach to delivering optimized energy efficient solutions for the SoC market (he leads ST’s architecture activities for energy-efficient, high-performance CPU/GPU implementations). In his presentation (click on image above to view it) entitled, “Energy Efficient Implementation of ARM® Cortex©-A57/-A53 Processor Cores in FD-SOI Process Technology”, Jacquet begins with an overview of the FD-SOI process technology as an enabler for high-performance/low-power design. He then highlights the low-power implementation and verification methodology developed with Synopsys, including results and best practices.