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ByAdministrator

RF-SOI – Foundries Weigh In On New 300mm Wafers for 4G/LTE-A, 5G and IoT. Plus a Look at the Innovation Pipeline – Part 2 of 2

As you may have read in the first part of this series, Soitec (the industry’s leading supplier of SOI wafers) says its 200mm RF-SOI wafers have been used to produce over 20 billion chips, and the company is now in high-volume manufacturing of a 300mm version of its wildly successful RFeSI line (see press release here).

So far it’s been all about RF front-end module – aka FEM – chips that handle the back-and-forth of signals between the transceiver and the antenna, originally in 2G and 3G phones. For 4G/LTE-A (and 5G when that hits), there were new wafer innovations – and now 300mm wafers.

The newest RF-SOI wafers, Soitec’s RFeSI90 series (available in both 200mm and 300mm diameters), offer higher levels of performance such as better uniformity, which chip designers need to achieve greater control of transistor matching in analog designs. Plus with the new wafers designers can use thinner transistors and additional process options to improve RonCoff performance, the figure of merit that’s used to rate the performance of an RF switch. For Soitec customers (and really, anyone doing FEMs these days is a customer), all these advances plus the large supply of 200mm and 300mm wafers means that they can expand their production capacities for RF-SOI devices and produce more highly integrated ICs.

GlobalFoundries, for example, sang the praises of 300mm wafers for RF-SOI at a recent SOI Consortium forum in Tokyo. Here’s a slide from Peter Rabbeni’s talk, (he’s GloFo’s Sr. Director RF Product Marketing and Biz Dev), RFSOI: Defining the RF-Digital Boundary for 5G (you can get the full presentation here):

GloFo_RFSOI_300mm_Tokyo2016_slide24

Courtesy: SOI Consortium and GlobalFoundries

As you see in the slide above, RF-SOI champion Peregrine Semiconductor introduced the industry’s first 300mm RF-SOI technology – that was back in July 2015. Dubbed UltraCMOS® 11, it’s built on GlobalFoundries’ 130 nm 300mm RF technology platform (read about it here).

Looking forward, GF’s Rabbeni noted, “Significant R&D has been done in evaluating the application of SOI to 5G architectures, with very positive results. SOI holds great promise in delivering on the key requirements of 5G systems.”

TowerJazzPanasonic_RFSOI_300mm14

Courtesy: SOI Consortium and TPSCo

Also at the Tokyo event, Kenji Tateiwa, General Manager of R&D Strategic Planning for TPSCo (that’s TowerJazz/Panasonic), gave a great presentation on 300mm RFSOI Development toward IoT Era. 300mm RF-SOI, he noted, “has room to run.”

European Program Pushes Innovation Pipeline

For Soitec, of course, work on future generations of RF-SOI substrates continues unabated. You can be sure they’ve got a product roadmap focused on continued innovation and cost effectiveness for future mobile communication markets.

But in addition to working on its RF-SOI roadmap internally, Soitec is leading an international program to further develop the technology in collaboration with 16 partners from five European countries, representing the entire electronics value chain from raw materials to finished communication products. The REFERENCE Project, awarded in a call for projects by the Electronic Components and Systems for European Leadership (ECSEL) group ─ aims to create a European competitive industrial ecosystem based on RF-SOI.

Over the next three years, the REFERENCE Project expects to innovate new materials, engineered substrates, processes, design, metrology and system integration that pave the way for 5G wireless communications. The R&D and demonstration objectives for 4G+/5G technologies include Soitec’s development of RF-SOI substrates, and the production of RF-SOI devices at two major European semiconductor foundries. These advances will contribute to RF-SOI’s growing use in three targeted applications: cellular communications/the Internet of Things (IoT), automotive and aeronautics , including pioneering new frequency bands.

Soitec is at the forefront of European innovation and we are very happy to be part of this very important European research project involving key partners beyond our direct customers,” said Nelly Kernevez, partnership director at Soitec. “This initiative allows us to build the European Union’s RF community, consolidate our vision of what the future can be, and leverage proven material technology to create RF communication solutions for tomorrow.”

The wireless world will keep progressing by leaps and bounds over the next few years. And it’s looking like ever-advancing RF-SOI substrates will be the springboard. Stay tuned!

ByAdele Hars

Now also on 300mm wafers and headed for 5G and IoT, RF-SOI’s going strong and stronger (>20 billion chips to date) – Part 1 of 2

Soitec, the industry’s leading supplier of SOI wafers recently announced it’s in high-volume manufacturing of a 300mm version of its wildly successful RFeSI line (see press release here).

What’s it all about? FEMs. RF front-end module – aka FEM – chips handle the back-and-forth of signals between the transceiver and the antenna. FEMs built on advanced SOI wafers are found in virtually every smartphone. Until now, the starting SOI wafers for all those RF FEMs were 200mm in diameter. But with demand continuing to increase, and the RF-SOI prospects for 4G/LTE-A (and then 5G) being very bright indeed, the bigger wafers were needed.

(Bear in mind that these RF-SOI wafers are not at all the same kind of wafers used in the RF and analog parts of an FD-SOI SOC. But because there’s still a fair amount of confusion about this, my ASN post, RF-SOI vs. FD-SOI with RF – What’s the difference? from a few months back sorted it out. If you missed it or you’d like a quick refresher, click here to read it.)

So, back to this announcement about the 300mm version of the RFeSI substrates. As the SOI wafer leader, Soitec’s got a lot of proprietary manufacturing technologies, and a boatload of experience with 200mm RF-SOI. High-volume manufacturing of 300mm SOI wafers isn’t new to them, either, since they’ve been doing that for over a decade.

Courtesy: Soitec

Courtesy: Soitec

But latest additions to the line, the advanced RFeSI90 wafers, required some really significant innovations. Soitec teamed up with UCL (you can read about that here) a few years ago on a breakthrough approach to SOI wafers for RF. This has opened the door for new enhancements that enable more highly integrated ICs for 4G/LTE-Advanced communications and the next generation of wireless technologies, including 5G.

20 billion RF-SOI FEMs, and counting

It so happens that the RFeSI 300mm wafer announcement comes just as Soitec reports that they’ve sold over a million 200mm RF-SOI wafers since 2009. Those million RF-SOI wafers have yielded about 20 billion FEMs. That means Soitec’s RF-SOI substrates are now integral in manufacturing antenna switches, antenna tuners, as well as some power amplifiers and WiFi circuits for the smart phone and related mobile markets. In fact they’re used by all the leading RF semiconductor companies to address cost, performance and integration needs for 3G and 4G/LTE mobile wireless.

Soitec_Aspar

Bernard Aspar, SVP Communications & Power BU, Soitec

Bernard Aspar, Sr. VP of Soitec’s Communication & Power Business Unit, is particularly pleased with their RF success. “The widespread use of Soitec’s materials technology in existing 3G and 4G portable communications demonstrates the important role of RF-SOI in high-volume, cost-sensitive applications such as cellular phones, tablets and other fast-growing markets involving mobile internet devices,” he said. “Now the high-volume availability of our newest 300mm RF-SOI offering enables our customers and their customers to continue to deliver higher performance while giving them access to foundries’ larger global production capacities and more manufacturing flexibility.”

200mm grows, too

To be sure, 200mm is still going strong and stronger, so Soitec is also increasing its 200mm production capacity. What’s more, last fall Soitec teamed up on a 200mm wafer manufacturing deal with Shanghai-based Simgui, which uses Soitec’s Smart CutTM technology to produce SOI wafers for its own RF, power and automotive customers in China, as well as manufacturing on an OEM basis for Soitec customers worldwide (read about that here).

Meanwhile, over the past 18 months Soitec has been delivering 300mm RFeSI90 wafer samples for product qualification. They note that key partnerships with fabless semiconductor companies and foundries have been instrumental in achieving the production milestones and outstanding performance levels of Soitec’s new 300mm RF-SOI product. In fact to make sure that customers get the performance they need, last year Soitec engineers even developed a way to predict the performance their wafers would provide (if you missed it, you can read more about that here).

To find out why some of the leading foundries and chipmakers have chosen to go with a 300mm RF-SOI wafer solution, and what’s in the RF-SOI substrate innovation pipeline, click here to read part 2 of this article.

ByGianni PRATA

RF-SOI Innovator JP Raskin (his team’s work is in your smartphone) Awarded Blondel Medal

Raskin_BlondelMedal2015_RFSOI

Professor Jean-Pierre Raskin (right) receiving the Blondel Medal for his industry-changing work on RF-SOI. Jury president Professor Pere Rocal I Cabarrocas (left) of the Ecole Polytechnique – Université Paris-Saclay presented the prize.

RF-SOI substrate guru Jean-Pierre Raskin, whose team at UCL* has driven the technology behind the most advanced wafer substrates for RF applications, has been awarded one of the highest honors in electronics: the prestigious Blondel Medal. The technology he pioneered is now in virtually all the world’s smartphones, and used by just about every RF foundry on the planet.

Dr. Raskin’s team first demonstrated a radical new approach (dubbed “trap rich” at the time) for improving the RF performance of high-resistivity (HR) SOI substrates back in 2003. Teams from UCL and Soitec then worked together on the industrialization, making it commercially available in SOI substrates for RF applications.

ASN readers will recognize this work from a 2013 article Dr. Raskin co-authored, Soitec and UCL Boost the RF Performance of SOI Substrates.

The result was a new wafer substrate Soitec named eSI, for enhanced Signal Integrity, and it’s been wildly successful. In fact Soitec estimates that more than one billion RF devices are produced each quarter using their eSI wafers. It’s been used for 2G, 3G and now 4G and LTE. With the advent of LTE-Advanced (aka LTE-A), 5G and Wi-Fi 802.11.ac (aka Gigabit Wi-Fi), the latest iterations of the Raskin team’s technology are in Soitec’s most advanced eSI90 wafers.

The Blondel Medal is the highest honor awarded by the SEE (the French Society for Electricity, Electronics, IT and Communications Technologies). It recognizes a researcher under 45 years old who has authored works or recorded exceptional achievements that have contributed to the advancement of science in Information and Communication Technology.

~ ~

*UCL is the Université catholique de Louvain in Belgium. Click here to read more about Dr. Raskin’s research group.

ByAdministrator

RF-SOI: Already in Every Smartphone, New Opps Abound in IoT (SF Workshop Part 3 of 3: IBM, ST, GF and more)

RF-SOI is already found in virtually every new smartphone out there, so the RF-SOI session of the recent FD-SOI/RF-SOI Workshop in San Francisco focused on long-term growth and further opportunities.

In case you missed it, ASN already covered the SF Workshop’s FD-SOI presentations (Samsung, ST and the EDA houses – click here for that post) and the panel discussion (where we learned Cisco is working on an FD-SOI chip – click here to read that post). As we mentioned there, the workshop was a huge success, with over 150 people from over 80 companies in the audience.

The presentations are becoming available on the SOI Consortium website, so keep checking there. (Also, if you want to know more about how the special wafers for RF-SOI solve design challenges, Soitec contributed an excellent ASN article a couple years ago – click here to read it.) But for now, here’s a brief recap of the RF-SOI presentations.

IBM

IBM has been offering RF-SOI foundry services since 2007 and recently said it shipped more than 7 billion RF-SOI chips in the last 3 years (read more about that here). Clearly they are experts in this business. In his talk, RF-SOI: Redefining Mobility and More in the Front-End, Mark Ireland, VP of Strategy and Business Development, Microelectronics Division, IBM Systems & Technology Group, said that LTE is the fastest developing mobile system technology ever. A big driver is mobile video: the CAGR there is 66% over the next five years, and it’s happening on both high-end and low-end smartphones.

IBM_RFSOI_LTE

 

Next comes IoT as an RF-SOI driver, and he gave a roadmap and examples.

IBM_RFSOI_IoT

He also looked at demand for RF-SOI wafers, which are typically 200mm, but he noted that 300mm is starting to sustain growth, too.

IBM_RFSOI_wafers_lowres

(You might also want to also refer to the IBM RF-SOI presentations given recently in Shanghai and Tokyo.)

ST

In her presentation entitled, ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration, Laura Formenti, Infrastructure and RF-SOI BU Director, STMicroelectronics focused on front-end module (FEM) integration (ST contributed an excellent article on this to ASN last summer – you can read it here). She made the link between new opportunities in RF-SOI and new developments by Soitec in RF-SOI wafers.

ST_RFSOI_roadmap

Putting power amplifiers (PA) on RF-SOI is starting to happen, and she provided data showing that they’re now closing in on GaAs in terms of performance.

ST_RFSOI_PA

ST is offering H9SOI_FEM on a foundry basis and as a partner. They can deliver prototypes within three weeks, and provide full integration up to packaging. (While you’re waiting for this presentation to be posted on the SOI Consortium website, you might want to refer to a similar presentation given recently by ST in Tokyo.)

GlobalFoundries

In SOI: An Enabler for RF Innovation and Wireless Market Disruption, Peter Rabbeni, Director of RF Segment Marketing at GlobalFoundries, focused on the value of SOI in RF, and explained why it presents an important opportunity for innovation at the system level.

GF_RFSOI_why

GF is the foundry partner for Peregrine (now part of Murata), and he showed how the GlobalONE PA integration is an excellent example of innovation opportunities.

GF_RFSOI_Peregrine

With an example of tunable filters, he also posited that the combination of FD-SOI and RF-SOI is a way to create disruption in wireless markets.

GF_RFSOI_FDSOI_filters

 

Incize

Incize is a spin-off of UCL in Belgium, which is a powerhouse in RF characterization. In fact, Soitec’s trap-rich SOI wafers, which are now being commercialized under the eSI moniker and launching a veritable RF revolution, were developed in partnership with UCL (you can read about that here). In his presentation entitled RF SOI: from Material to ICs – an Innovative Characterization Approach, Incize CEO Mostafa Emam explained non-destructive characterization for RF. Incize is currently working with eight customers, including wafer manufacturers. He highlighted the value of RF-SOI, and showed the characterization of Trap Rich vs. previous generations of high-resistivity (HR) SOI.

Imec

Barend Van Liempd, PhD Researcher at IMEC (Perceptive Systems dept.) / Leuven & Vrije Universiteit Brussel (VUB) (ETRO dept.,) gave a talk entitled Towards a Highly-Integrated Front-End Module in RF-SOI Using Electrical-Balance Duplexers. (He also presented this in a paper at ISSCC a few days prior.) He covered a highly integrated FEM program at Imec based on IBM technology and Electrical-Balance Duplexers.

More Workshops Coming

If you’d like to learn more about RF-SOI and/or FD-SOI, members of the SOI Consortium have been organizing these workshops around the world for the last six years (all the presentations from all the workshops are available here) and each one builds the momentum. But the workshops over the last six months (in Shanghai, Tokyo and now San Francisco) have taken that momentum to new levels. So keep an eye out for upcoming events throughout the coming year, where more and more users will be sharing their FD-SOI and RF-SOI design experiences.

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How SOI wafers for RF predict LTE-A/5G device performance

Soitec has developed an innovative metrology and metric for ensuring that devices built on our latest SOI wafers for RF will meet the draconian demands of LTE-Advanced (LTE-A) and 5G network standards.

For smartphones and tablets to handle LTE-A and 5G, they need RF devices with much higher linearity than those running over the current 2G, 3G, 4G and LTE network generations. These next generation network standards require mobile devices to support more bands, higher frequency bands, and emission and reception on adjacent bands with downlink and uplink carrier aggregation. (Carrier aggregation refers to the simultaneous reception of multiple frequency bands to improve data throughput.)

Soitec recently announced eSI90, our newest generation of trap-rich, high-resistivity SOI wafers for LTE-A and 5G. eSI90 extends our existing line of eSITM (enhanced Signal Integrity) wafers, the first generation of which are currently being used by leading manufactures to produce more than a billion RF devices every quarter.

This article gives an overview of how Soitec developed a new metric using innovative metrology on its wafers in order to predict the RF performance of final devices manufactured on eSI substrates. (Readers wanting greater detail can also consult our complete white paper on the subject, which is freely available to download here.)

Wafer specs evolve to meet new standards

To address the different communication standards and functions used in front-end modules, Soitec, the leader in SOI technology, has developed two flavors of RF-SOI products – high-resistivity (HR)-SOI and Enhanced Signal Integrity TM (eSI) SOI – both of which are compatible with standard CMOS processes. While standard HR-SOI wafers (which we introduced over a decade ago) are capable of meeting 2G or 3G requirements, eSI SOI can achieve much higher linearity and isolation specifications, allowing designers to address some of the most stringent LTE requirements. (We detailed how advanced RF design challenges are solved by eSI wafers in a 2013 ASN article – you can still read it here.) This paves the way for integrating more functions on a device with better RF performance at competitive cost.

eSI_SoitecUCLwafer

Soitec’s enhanced Signal Integrity™ (eSI) wafers integrate a trap-rich layer under the insulating BoX in a high-resistivity (HR) SOI wafer (Image courtesy of Soitec)

 

eSI wafers leverage the addition of a “trap-rich” layer to high-resistivity (HR) SOI wafers, an approach that was developed by UCL and Soitec (that project was covered in an ASN piece explaining the technical details at the time – you can read it here).

 

Change at all levels

The IIP3 linearity requirements for 3G are +65dBm. For LTE, they increased to +72dBm, and for LTE-A, they are over +90dBm. For RF designers, this has added substantially to the complexity of RF Front-End Modules (FEMs), and entails multiple changes for each of the main functions: switches, power amplifiers, power management and antenna tuners.

RFSOI_FEM_3G

Example of Front-End Module Block Diagram for 3G

RFSOI_FEM_LTE

Example of Front-End Module Block Diagram for LTE

 

These latest front-end modules need to support more bands, higher frequency bands from 700 MHz to 3.5 GHz, larger bands from 20 MHz to100 MHz and carrier aggregation downlink and uplink, sometimes on adjacent bands. This means:

  • A proliferation of switches on top of the antenna switch including diversity, power-mode and antenna-swapping switches
  • Advanced, tunable power-amplifier architectures to achieve compact and cost-effective multi-mode, multi-band transmission in a single broadband power amplifier
  • Advanced power management: with an envelope-tracking system approach, the efficiency of broadband power amplifiers will be close to or as good as that of single-band power amplifiers
  • Advanced wide-band antenna: with an antenna-tuner system performing either impedance matching and/or aperture tuning, an antenna can efficiently cover bands with frequencies from 700 MHz to 3.5 GHz with optimum efficiency and a smaller footprint

To meet the required performance, many changes are happening at all levels, from systems, architectures, design, manufacturing processes, devices – right down to where it all starts: the substrates. The substrates on which RF devices are manufactured have a significant impact on the level of performance that the final chips will be capable of achieving.

Characterizing eSI wafers

To quantify the performance designers can expect from an eSI SOI substrate, Soitec has now developed an innovative characterization method based on spreading resistance profiling (SRP), which can predict the 2nd harmonic distortion (HD2) performance of a coplanar waveguide. This solution is used today throughout the Soitec eSI product line to ensure the substrates will enable the expected RF performance in the finished devices.

We predict the RF harmonic distortion performance of the substrate immediately after the eSI SOI substrates are fabricated and before any devices are manufactured on them. This prediction is provided through a metric we call the harmonic quality factor (HQF).

HQF correlates with the second harmonic distortion generated from a 900-MHz signal applied to a coplanar waveguide (CPW) deposited on the substrate.

The CPWs are implemented on sample test wafers by depositing aluminum metal lines on the buried oxide of eSI SOI wafers after the Smart Cut process has been completed and the top silicium removed.

Then a 900-MHZ fundamental tone is applied on one end of the CPW line and the HD2 signal is measured at the other, providing a value of the HD2 generated by the substrate. Then, using the same wafers, a Spreading Resistance Profiling (SRP) technique measures the resistivity of the material at different depths under the buried oxide.

Next, we use a proprietary algorithm to compute the series of measures. The algorithm, tuned to match various HD2 values, takes into account the resistivity of the substrates weighted by the depth of the measure, and gives us the HQF.

Soitec has implemented this metrology on its production eSI SOI wafers and is sampling products to carry the HQF measurement.

To address different market requirements, we set our HQFmax specification at -80 dBm for eSI-G1 (first-generation eSI product) and at -90 dBm for our eSI90 (second-generation eSI product).

Soitec_RFSOI_eSI90_HQF

HQF specifications for Soitec’s 1st and 2nd generation eSI products (eSI-G1i and eSI90, respectively) correlated with linearity requirements.

Conclusion

HQF metrology, conducted at the substrate level, provides a reliable measure of the finished devices’ RF performance. It is now being used by Soitec to report the expected RF linearity performance of ICs manufactured with RF-SOI substrates.

As a solution addressing the current and next generation of RF standards, eSI SOI wafers are enabling this market by meeting some of the most difficult LTE and LTE Advanced linearity requirements. Soitec is able to provide its customers with the eSI SOI substrates that meet their desired level of RF performance.

ByAdministrator

LTE-A/5G: Bring it on. Next-gen Soitec eSI90 wafers predict & improve RF performance.

The folks at SOI wafer maker Soitec have announced an amazing update to their RF wafer line-up, with what they’re calling their eSI90 substrate (read the press release here). As you might expect, it improves on their terrifically successful line of substrates for the RF chips in smartphones and other mobile devices. And now with this latest substrate, they’ve developed metrology that allows designers to predict the linearity of finished RF devices, ensuring they meet the demands for next-gen networks.

SOI wafers for RF are mainly 200mm (8”) in diameter. Soitec CEO Paul Boudre says they’ll continue to run at full capacity in 2015-2016. Additional wafers will also be available through Soitec’s partnership with Simgui in China.

(Courtesy: Soitec. (C) photo Christian Morel / www.morel-photos.com)

(Courtesy: Soitec. (C) photo Christian Morel / www.morel-photos.com)

How successful is this line? “Today, we estimate that more than one billion RF devices are produced each quarter using our eSI wafers,” says Dr. Bernard Aspar, senior vice president and general manager of Soitec’s Communication & Power Business Unit.  That’s for 2G, 3G and now 4G and LTE.

But with the advent of LTE-Advanced (aka LTE-A), 5G and Wi-Fi 802.11.ac (aka Gigabit Wi-Fi), RF designers need a whole lot more linearity in finished devices. That’s where eSI90 comes in.

Why? We’re looking at a 10x increase in smartphone data traffic (much of it due to high-def video) between 2013 and 2018, with average connection speeds jumping from 4Mbps to 7 Mbps.

SOIwafers_Soitec_lowres

SOI wafers. (Courtesy: Soitec)

But to achieve the throughput needed, designers are faced with draconian linearity requirements and far more complex front-end modules (FEM). The wafer substrate they start on has a major impact on the performance level of the final devices.

Seeing this coming, a few years ago Soitec teamed up with experts at the Université catholique de Louvain (UCL). Leveraging Soitec’s Smart Cut™technology, they developed and industrialized the addition of a “trap-rich” layer in high-resistivity (HR) SOI wafers (if you missed it, they wrote an excellent ASN piece explaining the technical details at the time – you can read it here).

The first generation of these trap-rich HR SOI wafers, which Soitec called eSI (for enhanced Signal Integrity), was a tremendous success from the get-go. Designers loved that the wafers enabled relaxed design rules, reduced process steps and gave them highly competitive performance and die cost, including a smaller area per function (well explained here).

So here’s what’s new about the new eSI90 wafers: they exhibit higher effective resistivity than first-generation eSI wafers, enabling a 10-decibel (dB) improvement in linearity performance in RF front-end modules to address the stringent new requirements of LTE-A smart phones.

Those eSI90 SOI wafers are designed to improve the RF performance of mobile communication components such as high-linearity switches and antenna tuners that are integrated in high-end smart phones for LTE-A networks using carrier aggregation. This enables multiple LTE carriers to be used together, providing higher data rates to enhance user experience.

To ensure that the new wafers would deliver on their promise, the Soitec team developed a new metrology metric, the Harmonic Quality Factor (HQF), to predict the expected RF linearity of finished ICs. We’ll have a more in-depth explanation of how this works coming up in ASN from the Soitec team. But for now, designers will appreciate that HQF correlates with the second harmonic distortion value of a coplanar waveguide deposited on the substrate. The new eSI90 wafers’ HQF maximum value is set to -90 decibel- milliwatts (dBm) compared to -80 dBm for first-generation eSI substrates. The lower limit on eSI90 wafers enables chipmakers to take advantage of design and process improvements to increase the RF performance of their chip designs and to meet MIMO (Multi-Input Multi-Output) and Carrier Aggregation LTE-A requirements, providing faster data connections.

The new eSI90 substrates are already under evaluation at leading chipmakers and foundries. Production-ready samples are now available from Soitec.

When it comes to next-gen mobile design, innovation really does start at the substrate level.