If you’re going to Semicon West this year, be sure to attend the SOI Consortium’s workshop on how IoT is driving the SOI supply chain. There’s a great line-up of speakers – see the program below.
IoT means many things to many people but everyone agrees it’s here and growing quickly. IoT, including machine learning and movement to the edge, is fueling innovation as the high compute and ultra-low energy requirements are pushing technology to deliver on these needs. The well-known characteristics defining IoT of “Sense”, “Compute”, and “Act” put additional burden on technology to full these requirements across a variety of use cases and environments without sacrificing reliability or quality.
All the various forms of SOI technology from FD-SOI to High-Voltage to RF-SOI, are uniquely situated to deliver on the promise of today’s as well as tomorrow’s IoT roadmap. The supply chain for all forms of SOI technology is in place. This workshop will discuss the current and future solutions from a supply chain perspective.
Speakers include experts from SOI Consortium members Applied Materials, NXP, GlobalFoundries and Soitec.
Entitled The Internet of Things, Driver of the SOI Supply Chain, the workshop will take place at the Moscone Center South, Wednesday July 10th in Room 301. It will run from 1 pm until 4:30 pm. Anyone and everyone who is registered for Semicon West is welcome. Here is the sign-up page.
It’s a great program:
1:00pm – Welcome by Semi
1:10pm – IoT/AI/Edge Market – Using SOI Through-out, Jon Cheek, Senior Director, NXP
1:35pm – The SOI Opportunity, Manish Hemkar, Director, Semiconductor Products Group, Applied Materials
2:00pm – The Foundry IP Ecosystem, Jamie Schaeffer, Sr. Director, GlobalFoundries
2:25pm – Engineered Substrates – Enabling the IoT Revolutions, Eunseok Park, Director, Emerging Technology in Strategic Marketing, Soitec
2:50pm – Enabling the SOI Era, Thomas Uhrmann, Head of Business Development, EVG
3:15pm – Panel: The Internet of Things, Driver of the SOI Supply Chain, Moderator: Carlos Mazure, Chairman, SOI Industry Consortium. Panelists include:
4:05pm – Closing remarks, Carlos Mazure, Chairman, SOI Industry Consortium
4:20pm – End
This is a great chance to learn more about SOI and the SOI Consortium. Don’t miss it!
And while you’re at West, you should also check out a related event. SOI Consortium member Leti will be teaming up with Fraunhofer for a workshop entitled New Paradigms in Microelectronics–Providing R&D for the 21st Century. That happens at the nearby W Hotel in San Francisco on Tuesday, July 9th at 5:00pm. Click here for more information on that.
Before summer’s no more than a twinkle in our eyes, let’s take a moment to catch up on a key event where FD-SOI took center stage: Leti Innovation Days. French research powerhouse Leti was celebrating 50 years of innovation, so it was a real gala event.
FD-SOI and other SOI technologies were seen and heard throughout the presentations and in the exhibition spaces. But there were a couple of things that were especially interesting that I’ll cover here in ASN. In particular, a panel discussion with GF, Synopsys and Qualcomm; and the big announcement from Leti and Fraunhofer supporting continued FD-SOI development.
(There were also some great info about body biasing in FD-SOI, but we’ll save that for a future post.)
The Panel & More
A session on Micro-nano Pathfinding and the Digital Revolution featured a fascinating panel discussion on Future Applications and New Technologies. As Rajesh Pankaj from Qualcomm, Alain Mutricy from GF and Antun Domic from Synopsys discussed the prospects, FD-SOI quickly took center stage.
Here are some FD-SOI observations from GF’s Alain Mutricy:
It’s planar, so it’s not hard to design in.
It’s the only technology that can get down to 0.4V, and it has the lowest leakage/cell. That will be key for all mainstream applications (except high-end servers) for at least a decade or two.
12 FDX with forward body bias (FBB) will get 7nm FinFET performance.
They’re looking forward to broad FD-SOI adoption. It will enable the next wave of technology and mobile devices.
Synopsys’ Antun Domic noted that:
Currently, 50% of silicon area comes from just 3 or 4% of designs. FD-SOI makes design simpler, so the EDA companies are looking for it to open the door to more designs.
From a design perspective, three thresholds was standard, but that’s not enough. Place and route could stretch to 10 or 15 corners. FD-SOI simplifies tool flow and cuts mask costs. It’s less complicated than you think.
That tech session, btw, began with an excellent testimonial by Leti partner, Soitec. (Remember: the technological innovation that enabled modern SOI wafers came out of Leti and was industrialized by Soitec.) Check out the snapshot below to get an idea of all the areas that SOI-based technologies address.
Leti, Fraunhofer & FD-SOI
The big piece of news to come out of Leti Days is that Leti is teaming up with Fraunhofer to “…strengthen microelectronics innovation in France and Germany” (read the press release here). The agreement was signed by Leti CEO Marie Semeria and Fraunhofer Group for Microelectronics Chairman Hubert Lakner at an official ceremony. A lively the press conference followed. Prof. Lakner emphasized that they are working on a common European roadmap, with a clear plan for collaboration on FD-SOI. Europe, he said, is a good idea, and working together, France and Germany can do a lot for industry. For FD-SOI, Leti is focused on the front-end, and Fraunhofer is working on the back-end.
Working together, they can elevate pillars like FD-SOI from the country level to the European level, noted Dr. Semeria. And that puts them in a more elevated position for EC funding initiatives such as an upcoming IPCEI – which stands for Important Project of Common European Interest.
Initially, however, the focus will be on extending CMOS and More-than-Moore technologies to enable next-generation components for applications in IoT, augmented reality, automotive, health, aeronautics and other sectors, as well as systems to support French and German industries. A second phase extending to other partners and countries is possible. We’ll keep you posted.
In closing, I’m sure you’ll all join me in extending hearty congratulations to Leti on their 50th anniversary. And here’s to their next 50 years of innovation – can you imagine what that might bring? It rather boggles the mind, doesn’t it?
The Heterogeneous Technology Alliance (HTA), a coalition of top European R&D organizations, is offering an SOI-MEMS platform. Looking to bridge the gap between academia and industry, this technological platform pools the SOI-MEMS expertise, capabilities and fabrication facilities of Leti (France), Fraunhofer (Germany), CSEM (Switzerland) and VTT (Finland).
The main focus of HTA (click here for the website) is the further development of innovative Smart Systems. SOI-MEMS is typically used for silicon oscillators, microphones, speakers, compass, navigation, motion sensors, sensors and actuators, energy harvesting, micro fuel cells, microfluidics and other deep reactive-ion etched micro structures. A recently issued brochure gives an overview of the offering.
The HTA is active at all levels of Smart Integrated Systems Solutions: from applied research on materials, processes and equipment through the fabrication of devices and components to the development of new products and services. Development and small-scale production cleanrooms for micro-electronics, MEMS, power electronics and analogue components is available. Wafer handling capacity encompasses wafer sizes ranging from 100, through 150 and 200 to 300 mm.
A one-stop shop for complete system solutions, the HTA guarantees simple access to an enlarged portfolio of technologies and is structured to facilitate technology transfer to European and non-European companies. In addition to working with large industrial partners, the HTA offers services specially suited for small and medium-sized companies. With a combined staff of more than 5,000 scientists and a portfolio of more than 3,000 patents, the HTA is de facto the largest European organization in the field.
III-V wafer bonding has enabled a new world record for the conversion of sunlight into electricity, announced the Fraunhofer Institute for Solar Energy Systems ISE, Soitec, CEA-Leti and the Helmholtz Center Berlin. Creating a new solar cell structure with four solar subcells, the team took the lead after only over three years of research, entering the roadmap with a new record efficiency of 44.7%. This indicates that 44.7% of the solar spectrum’s energy, from ultraviolet through to the infrared, is converted into electrical energy. This is a major step towards reducing further the costs of solar electricity and continues to pave the way to the 50% efficiency roadmap. Wafer bonding plays a central role, as it enables the connection of two semiconductor crystals that otherwise cannot be grown on top of each other with high crystal quality. This produces the optimal semiconductor combination for the highest efficiency solar cells.
A few weeks prior, Soitec announced the launched of a new solar-energy concentrated photovoltaic (CPV) module featuring 31.8% efficiency, the highest of any commercial module being mass produced today.