Dolphin Integration, a partner in the ENIAC THINGS2DO European FD-SOI project, showcased its achievements with PowerStudio™ during the project final review. Power Studio is Dolphin’s cutting-edge EDA tool for safe Power Regulation Networks implementation.
THINGS2DO, which stands for THIN but Great Silicon to Design Objects, was a 4-year, >€120 million EU project (85% industry-funded) with over 40 partners that just finished up at the end of 2017. The goal was to build a design & development ecosystem for FD-SOI. The project funded and supported the development of major FD SOI-based IPs and ASICs as well as EDA tools. (Another recent THINGS2DO announcement was Dream Chips’ ADAS SoC fabbed in GlobalFoundries’ 22FDX technology — read about that here.)
“Being involved in the THINGS2DO project was an opportunity for Dolphin Integration to start introducing FD-SOI in its automatic design methodologies,” said Frederic Poullet, Dolphin Integration’s CTO (read the press release here). “Dolphin Integration plans to offer a full suite of tools allowing its customers to implement right-on-first-pass Power Regulation Networks.”
The company notes that THINGS2DO also proved that low power consumption makes FD-SOI a perfect fit for IoT and automotive applications. For instance, dynamic control of threshold voltage can be used to compensate for temperature variations, and to drive speed improvements by 200% in ultra-low voltage applications.
Dolphin Integration provides energy efficient IPs and ASIC services dedicated to the low-power application market and supports its internal teams with tailor-made software tools. To address the specific needs of its customers in low-power design, Dolphin developed PowerStudio™, a global solution for the optimization of Power Regulation Networks (PRNet) to be used at an early stage of the SoC design process. In particular, it addresses new design challenges in noise and power supply integrity.
The first module of PowerStudio™ will also embed architecture optimization features at the schematic level, in terms of FoM-based cost optimization, mode management, margin cuts and integrability rate-based risk optimization.
Btw, Dolphin Integration Director Frederic Renoux gave an excellent great presentation at an SOI Consortium event in Nanjing, China last year, entitled Embedding power regulation & activity control networks for best SoC PPA.
Dolphin Integration joined Global foundries’ FDXcelerator™ Program last year (read the press release here) to streamline design in 22FDX®. “Our comprehensive and robust library of voltage regulators, power gating cells and logic modules, enables to deal cost-effectively and securely with power distribution, power gating, power monitoring and power control of any SoC design in 22FDX,” Michel Depeyrot, Dolphin Integration’s Chairman, said at the time. “As connected devices sleep most of their time, users of 22FDX also benefit from our ultra-low power and accurate oscillators to design an always-on RTC which consumes as little as 60 nA.”
The MCU at the heart of Sony’s new smart-sensing SPRESENSE™ for IoT is built on FD-SOI. Why? Low operating voltage and low power consumption, of course! Sony’s got two cool new products going on sale in July 2018: the SPRESENCE main and extension boards for IoT applications, equipped with a smart-sensing processor (read the full press release here). A CXD5602PWBCAM1 camera board for sensing cameras will go on sale in August. All were on display at the SF Maker Fair ’18, where they were an instant hit.
Spresense is powered by Sony’s FDSOI-based CXD5602 MCU (ARM Cortex-M4F × 6 cores), with a clock speed up to 156 MHz. The main board utilizes a multi-CPU structure equipped with Sony’s state-of-the-art GNSS (Global Navigation Satellite System – which they talked about at the most recent SOI Symposiums in SF and Tokyo) receiver. A variety of systems for diverse applications, including drones, smart speakers, sensing cameras and other IoT devices, can be built by combining these boards and developing the relevant applications.
The new board can be used to control a drone, for example, using GPS positioning technology and a high-performance processor, voice-controlled smart speakers, low-power consumption sensing cameras and other IoT devices, etc. It can also be combined with various sensors for use in systems that detect errors in production lines on the factory floor.
Good news: there are far fewer bigoted extremists out there when it comes to FD-SOI vs. FinFETs. People want the best technology for their application. It’s that simple. That’s a key piece of news from the updated survey by Dan Hutcheson, CEO of VLSI Research, which he presented in the afternoon session of the SOI Consortium’s 2018 SOI Symposium in Silicon Valley
The afternoon then featured presentations by foundry partners, which I’ll cover here.
Also in the afternoon were presentations by wafer-maker Simgui, some innovative start-ups leveraging FD-SOI for custom SoCs and the final panel discussion. I’ll cover those in Part 3 of this series.
BTW, if somehow you missed my coverage of the morning sessions about very cool new products and projects from NXP, Sony, Audi, Airbus and Andes Technology, be sure to click here to read it.
The presentations are starting to be posted on the SOI Consortium Events page – but some won’t be. Either way, I’ll cover them here.
A couple years ago at the annual SOI Symposium in Silicon Valley, Dan Hutcheson presented results of a survey he did (ASN covered it – you can still read about it here). At the 2018 event, he presented an update, which is now posted. You can get it here.
The FD-SOI roadmap and IP availability are no longer issues for decision makers, he found. The 14nm branch – do you go FinFET or FD-SOI? – is gone. “Fins and FD are complementary,” he observed. Most people said they’d consider using both and running two roadmaps, choosing whichever technology is appropriate to a given design.
From a transistor viewpoint, the top reasons to choose FD-SOI is that it’s better for analog and has lower leakage/parastics. It’s perceived as better for complex, high mixed-signal SoCs, and especially for RF and sensor integration. In fact, people see RF as the new mixed-signal, wherein FD-SOI is uniquely positioned for 5G and mmWave.
From a business viewpoint, FD-SOI is perceived to have real advantages. In particular, FD-SOI wins when it comes to keeping down design costs, manufacturing costs and time-to-market. IoT is still the hottest target market for FD-SOI, to which he adds high growth expected in automotive and medical.
With 20 tape-outs in 2018, Samsung is seeing an acceleration in its FD-SOI business. “The trend is healthy,” said Hong Hoa, SVP of the company’s foundry business. FD-SOI, he continued, is on a “differentiation path.”
Samsung’s 28nm FD-SOI process, called 28FDS is at full maturity with very strong yields. They’re seeing more customers and a wider range of applications. The design infrastructure, silicon-verified IP and methodologies are also all mature. They have optimal implementation and verification guidelines for body bias design, a body bias memory usage guide, and a body bias generator integration guide. The process supports Grade 1 automotive, and will be qualified for Grade 2 in a few weeks.
FD-SOI, Hoa reminded the audience, offers superior RF performance compared to both planar bulk and 14nm FinFET. The Samsung strategy is to first provide a base for for the FD-SOI process, then add RF and eMRAM. The base for 28nm was done in 2016; they added RF in 2017 and eMRAM this year.
The Samsung platform for IoT applications integrates both RF and eMRAM to support multi-function needs in a single platform. Lead customers are already working with eMRAM in their designs, he added. (BTW, Samsung has a really nice video explaining their eMRAM offering – you can see it on YouTube here.)
The basic PDK for the Samsung 18nm FD-SOI process (18FDS) will be available in September 2018, with full production slated for fall of 2019. It will deliver a 24% increase in performance, a 38% decrease in power, and a 35% decrease in area for logic. RF for the 18FDSplatform will be ready by the end of this year, and eMRAM beginning in 2019.
With design wins from 36 customers underway, 12 of which are taping out in 22FDX (GF’s 22nm FD-SOI process) this year, the market has validated FDX for differentiation, said GF SVP Dr. Bami Bastani. And indeed, designers are using it for a wide array of applications across North America, Europe, Asia/Pacific and Japan.
Customers in the North America are designing in 22FDX for NB-IoT, industrial, RF/analog, mobile, network switches and cryptocurrency applications. In Europe, it’s more or less the same plus automotive/mmWave, optical transmission, wireless BTS and AI/ML. In Asia Pacific/Japan the mix is similar to Europe.
Bastani sees the three big enablers as the the strengths of the roadmap, the ecosystem and multi-sourcing from Dresden and Chengdu (where they’re already equipping the cleanrooms). He also tipped his hat in acknowledgment to the partnership with FD-SOI wafer supplier Soitec, noting that they have gone the extra mile to match GF’s requirements.
So that was the first part of a great afternoon. As mentioned above, my next post (part 3) will cover a very informative presentation by wafer-maker Simgui on the markets in China, plus talks by some innovative start-ups leveraging FD-SOI for custom SoCs and the final panel discussion.
“The ecosystem is ready. The focus is now on applications and products.” And with those words, SOI Consortium Executive Director Carlos Mazure opened the annual Silicon Valley SOI Symposium. As promised, the day was packed with presentations about products on FD-SOI – some from big players like NXP and Sony, some from names new to the FD-SOI ecosystem like Audi and Airbus, and some from start-ups just getting into the game.
The event got excellent coverage in EETimes/EDN – including in their editions across the globe in China, Japan, Taiwan, India and more. Samsung, GF Ramp FD-SOI, heralded the headlines.
It was a full day of excellent presentations. In this post, I’ll chronicle the morning presentations. The next post(s) will cover the afternoon session. Note that as of this writing, the ppts are not yet posted on the SOI Consortium website, but many will be. Keep checking back under the Events tab, and look under “past Events”.
As semiwiki noted a few years back, Andes Technology is “…the biggest microprocessor IP company you’ve never heard of.” Based in Taiwan, Mediatek is one of their big customers; they’ve got a strong client base across Asia/Pacific, and are now making inroads into North America. Last year they announced with GF their 32-bit CPU IP cores had been implemented on GF’s 22FDX® FD-SOI technology.
In his symposium keynote, CEO Frankwell Lin said that in the test chip they’re doing with GF and Invecus, they’re seeing a 70% power savings compared with what they’d gotten in 28ULP. Their newest products are the N25 32bit and NX25 64bit RISC-V based cores, and in July they’ll announce a core that runs on Linux.
“With FD-SOI we’re enabling the future of embedded processing,” the always-quotable (and keynote speaker) NXP VP/GM Ron Martino told us. NXP’s i.MX7ULP, i.MX8, i.MX8X and i.MXRT are all FD-SOI based. They all share fundamental building blocks, so NXP can build platforms, scale and re-use IP. “It’s better than any technology I’ve worked on in my 30 years in the industry,” he said.
They’re seeing much higher performance with on-chip flash. And the RT “crossover” processor boasts 3x higher computing performance than today’s competing MCUs. This is going to be critical for edge computing going forward, to which end NXP is working very closely with foundry partner Samsung.
FD-SOI is not just helpful for the logic part of these chips – memory technologies also share in the benefits. They get much higher performance with on-chip flash. Leakage is cut by a factor of ten with biasing techniques, and the enhancements mean that memory can operate at very low voltages.
NXP is increasingly sophisticated with how they use body biasing, applying high-granularity techniques to independent domains in different parts of the chips. Getting sub-0.6 Vmin delivers value at multiple levels: on battery life, on total system cost, and on system enablement. Invest in body biasing if you want to get leadership results, advised Martino.
Edge computing – including machine learning and neural networks for things like image classification – is a big target, he continued. At the last CES they did a proof-of-concept “foodnet” where two appliances talked to each other without having to go to the cloud. In that case it was an i.MX8 in a fridge and an i.MXRT in a microwave, but he explained that the same concept can be applied to a car for driver awareness, where you don’t want to take the extra time for or don’t have a connection to the cloud.
iMX and FD-SOI enable scalable solutions, he concluded.
What’s a metal-bending company doing talking about electrons? asked Audi Project Manager Dr. Andre Blum. And why SOI? Well, for Audi, he said, SOI stands for Solutions, Opportunities and Innovation.
Audi is working on the various levels of autonomous driving, and they want it to be without design limitations. That means being able to hide sensors wherever they’re needed. They’ll create a cocoon around the car for the best driver experience. He showed a fun video Audi’s made to illustrate their concept – it’s the Invisible Man video, which you can check out on YouTube.
But those new architectures can’t up the power budget (think heat): rather they need to cut power drastically while increasing performance. And with FD-SOI, they see an opportunity to do just that, he said, while integrating the sensors.
Audi is one of 25 partners in a heavily funded (>100 million Euros) brand new EU Horizon 2020 program called Ocean12 (lead by Soitec). The launch was only May 1st 2018 (so as of today it doesn’t even have a website yet), and it will run for about 4 years. It is described by ECSEL (a public-private entity that puts together the big EU research projects) as an “opportunity to carry European autonomous driving further with FDSOI technology up to 12nm node”. One to watch!
For Airbus, it’s all about increased connectivity and communications that are trusted and secure, said company expert Olivier Notebaert. Since their chip runs are low, NRE – non-recurring engineering costs – are very important; and they need flexible systems.
SOI has a long history in aerospace – in fact that’s originally where it got its start, since it can handle radiation and is immune to latch-up. Notebaert says that even for Airbus, IoT is their future. The developments they pioneer will be part of it.
Airbus is a partner in the EU Horizon 2020 DAHLIA project – which stands for Deep sub-micron microprocessor for spAce rad-Hard appLIcation Asic. The project is, “…developing a Very High Performance microprocessor System on Chip (SoC) based on STMicroelectonics European 28nm FDSOI technology with multi-core ARM processors for real-time applications, eFPGA for flexibility and key European IPs, enabling faster and cost-efficient development of products for multiple space application domains. The performance is expected to be 20 to 40 times the performance of the existing SoC for space.”
According to another recent presentation, DAHLIA is prototyping an FPGA this year that will be in production in 2019.
For Sony GM Kenichi Nakano, FD-SOI has big potential for low-power products. And he should know. Sony has been an FD-SOI pioneer, using it as the basis for GPS chips that are now in a growing number of cool products, especially watches. They’re getting good feedback from the market and see good opportunities across a diversified global customer base, he said. Their CXD5603, for example, is the lowest power GNSS (GPS) chip worldwide. In mass production since 2015, it is now dominating world wearable markets like trackers — such the popular Amazfit line.
Running through their various FD-SOI based GPS offerings, he noted that the GPS is a pretty simple chip. But now customers are asking for more, like for it to work in the water (where a GPS typically doesn’t). So Sony has partnered with triathalon teams and are seeing good results.
With success, of course, comes greater demands: for greater accuracy, for more precise positioning in motion, for increased height accuracy, for even lower power – and Sony is meeting these demands with FD-SOI, in solutions like the new CXD5602. The CXD5602 product configuration covers audio/video/communications: key factors in IoT. A camera version is releasing this summer, as are main and extension boards. An LTE module will be released at the end of 2018.
And now they’re using those FD-SOI chips in audio applications. You’ll find it in the Xperia™ Ear Duo, he said. The MWC press release noted that Xperia Ear Duo “… is driven by Sony’s ultra-low power consuming “CXD5602” chip and a sophisticated multi-sensor platform, the “Daily Assist” feature will recognize time, location and activities to offer relevant information throughout the day – reminding you what time your next meeting is when you reach the office or narrating the latest news headlines.”
Also in that PR, Hiroshi Ito,Deputy Head of Smart Product Business Group at Sony Mobile Communications, said, “Ear Duo is the first wireless headset to deliver a breakthrough Dual Listening experience – the ability to hear music and notifications simultaneously with sounds from the world around you.” The highly anticipated wireless “open-ear” stereo headset started rolling out to select markets in Spring 2018. There’s a great info page with video here.
So that’s what we heard in the morning. My next post (or posts?) will cover the afternoon. That includes Dan Hutcheson’s excellent talk updating his FD-SOI survey, presentations from Samsung, Globalfoundries and Simgui, plus some from very cool start-ups, and the final panel presentation.
FD-SOI has hit Q1 with terrific momentum, both in terms of visibility into products and in press coverage. In case you missed them, here are three articles you should definitely read:
But, if you don’t have time to read them all right away, here are some highlights to tide you over til you do.
Ed Sperling at SemiEngineering sees FD-SOI adoption “… gaining ground across a number of new markets, ranging from IoT to automotive to machine learning, and diverging sharply from its original position as a less costly alternative to finFET-based designs.”
After recounting the advantages (with which ASN readers are well familiar), he notes that two things have changed in our industry. First, fewer and fewer companies can afford to design in the most advanced FinFET nodes. And second: there are enough emerging markets where power is critical, but there won’t necessarily be the billions of units per chip needed to amortize exorbitant design costs.
In particular, for FD-SOI adoption he cites, “…the inferencing stage of machine learning [note: that happens in “edge” devices], base-stations, IoT and IIoT, bitcoin mining, 5G, radar, and a variety of automotive applications.” (GF’s Jamie Schaeffer makes the technical case in the article for NB-IoT and automotive if you want more info.)
ST’s Giorgio Cesana makes an interesting point about body biasing (that I hadn’t hear before) re: uni-direction vs. bi-directional. Currently, he explains, body biasing is uni-directional – although you can use it now in such a way that is effectively bi-directional. However, after the 22nm node, it will become truly bi-directional, which will enable wider swings for power savings. (For those concerned about pre-mature chip aging, see the full article for explanations by experts from Soitec who explain why that’s not a problem after all.)
Cesana also points out that the kind of chips leveraging FD-SOI are not the kind of chips that will need to move to a new node every year. They’re looking for power savings, not shrink. Sperling goes on to make an interesting observation about Intel/MobileEye and power savings vs. shrink – by all means read what he has to say about that….
In conclusion, Sperling asserts that we are now witnessing a shift in the semi supply chain essentially dovetailing with the expansion of FD-SOI adoption and its ecosystem, wherein “…as new markets open up, chipmakers are finding themselves much closer to the application than in the past.”
All in all a great read – don’t miss it.
David Lammers (who you probably know from SST) wrote about products on FD-SOI for GF’s Foundry Files in 22FDX Shows IoT Traction at MWC 2018. A number of start-ups will be showing products on GF’s 22FDX (FD-SOI) technology at Mobile World Congress.
For example, Nanotel Technology is using 22FDX to “…reduce power consumption for its mixed-signal NB-IoT modem.” Lammers interviewed the company’s CTO, Anup Savla, who explained, “We have a digital engine, a processor, designed around IoT applications, where the emphasis is on low power and low leakage. With 22FDX there are knobs that are available to turn down the power and leakage. The opportunities to do that are unparalleled, and you just don’t get that kind of opportunity from bulk CMOS.” A significant part to this design is analog – which of course really benefits from FD-SOI.
Riot Micro on the other hand, has designed an all-digital cellular modem for LTE Cat-M and NB-IOT. There’s no DSP, and big parts of the chip can be shut down as needed to save power for long-term battery operation in the field (get more details in the full GF blog). Several major cellular carriers are on track to certify it this year, and a Middle Eastern customer plans to incorporate it into an emergency-alert system. The company’s CEO, Peter Wong told Lammers, “With 22FDX, the value proposition for us is potential power and area savings.” They also leveraged the growing 22FDX IP ecosystem to accelerate TTM.
Dream Chip Technologies, which as Lammers reminds us, showed their multi-core vision processor at MWC last year, says that now “…the design is providing European auto makers and Tier 1 automotive component suppliers with a platform from which they can create custom derivatives.”
Verisilicon, an SOI Consortium member and a major FD-SOI champion in China will be teaming up with GF show their dual-mode connectivity solutions (which we first heard about last year). GF and VeriSilicon have a suite of IP so that customers can create single-chip, low-power wide-area (LPWA) solutions that support either LTE-M (for the US) or NB-IoT (for Asia & Europe). The IP covers integrated baseband, power management, RF radio and front-end components.
Lammers also cited Anubhav Gupta, GF’s director of strategic marketing and business development for IoT, AI & Machine Learning. He said they’ve got customers taking older multi-chip designs and re-creating them as single-chip solutions in 22FDX for better performance and savings in area, power and cost. Gupta noted that with body biasing in digital designs, they can operate down to 0.4V with standby leakage currents of less than one picoamp per micron. And when embedded MRAM is used in tandem with on-chip SRAM, off-chip flash can be completely eliminated.
In a wide-ranging interview (see part 7, which focuses on FD-SOI), GF CTO Gary Patton told Anandtech’s Ian Cutress that, “FinFET is a great technology for [performance at any cost], but if you’re looking for something that is more in the consumer space, you need to balance performance with power and cost, you know FD-SOI is a clear winner.”
Patton told Cutress that they have working 12FDX devices in NY that are already close to reaching performance targets. They’ll be in risk production in early 2019.
Meanwhile in 22FDX, Patton talked about the different flavors, including RF, ULP, UL leakage and mmWave, and how well suited they are for target applications especially in automotive and IoT. Elsewhere in the interview he mentioned that potential customers in the cryptocurrency mining businesses are looking at 22FDX, and that ST will be using it to do some “incredible products”.
All in all – products and press – it’s a really fine Q1.
EDA companies Cadence, Synopsys and Silvaco all gave excellent presentations at the SOI Consortium forums in Nanjing and Shanghai.
Here’s a recap of what the Cadence folks said. (I’ll cover the Synopsys and Silvaco presentations in my next posts.)
At the Shanghai FD-SOI Forum. Dr. Qui Wang, VP & Chief of Staff, talked about FD-SOI Foundry Enablement: From Concept to Mass Production. Cadence, he reminded the packed ballroom, is not just EDA, but also system design enablement targeting verticals. “We’re ready!” he stated.
In the last three years, they’ve done a lot of work on FD-SOI, he said, even working with ARM, GF and Dream Chip on the demo board as a reference design for automotive or vision applications, to show real data to their customers. It uses a quad implementation of the configurable Tensilica Vision P6 core.
To simplify back biasing for the library folks, they worked with the foundries to create interpolations. And as Cadence is traditionally strong in RF/mixed-signal, there’s a new back-biasing tool to simplify board-chip communications, and make the bridge between power and thermal analysis.
Jonathon Smith, Director of Strategic Alliances at Cadence, presented Enabling an Interconnected Digital World — Cadence EDA & IP Update at the Nanjing SOI summit. As he explained, his job is to ensure that design customers can use Cadence tools effectively, not just with Cadence IP, but also with 3rd party IP for the foundry nodes.
He pointed out that the numbers for IoT predictions vary widely, and that industrial IoT (IIoT) will probably account for about 10% of the market. What is sure is that it will contain a large mixed-signal component (RF/digital/analog) and complex packaging.
His customers want to know how fast and easy it is to work in FD-SOI. “Cadence custom and digital tools are ready for FD-SOI,” he said. They have the PDKs and tech files, and the EDA tools are enabled. The reference flows (both digital and custom analog) are tested and ready (Cadence customers who use p-cells and RF look especially for a good mixed-signal flow).
Customers also ask for proof points, and want to know the number of tape-outs they’ve done, performance benchmarks for working silicon and proven IP: this is what gives designers confidence, he said. Examples like Dream Chip’s Computer Vision Processor Chip Design for automotive ADAS CNN applications in 22nm FD-SOI (which they announced at Mobile World Congress in 2017 – see the press release here) have really helped build confidence further, he observed. (In case you missed it, DreamChip presented at the Silicon Valley SOI event in April 2017 – you can get that presentation here.)
Cadence sees SOI as a driving force in IoT markets. They’ve also had some big digital wins recently, he added, and have made some major announcements with the foundries.
For example, in September, they announced that their set of Design for Manufacturing (DFM) tools (signoff solutions) are now qualified on Samsung’s 28nm FD-SOI. This enables customers to create complex, advanced-node designs for the automotive, mobile, IoT, high-performance compute (HPC) and consumer markets (read the press release here). The Samsung Foundry’s PDKs for 28nm FD-SOI are available for download now and incorporate the Cadence Litho Physical Analyzer (LPA), Physical Verification System (PVS) and Cadence CMP Predictor (CCP). In addition to signoff quality, the Cadence DFM tools offer an integration with the Virtuoso® platform and the Innovus™ Implementation System, providing designers with automated fixing capabilities and overall ease of use.
And in October, Cadence announced that its digital and signoff flow, from synthesis to timing and power analysis, supports body-bias interpolation for GlobalFoundries 22FDX™ (read the press release here). The Cadence® tools enable advanced-node customers across a variety of vertical markets—including automotive, mobile, IoT and consumer applications—to use GF’s FD-SOI architecture to optimize power, performance and area (PPA).
Cadence tools for ST’s 28nm FD-SOI foundry process were ready in 2016, btw – there’s a nice video testimonial from ST on power signoff, for example, which you can see here.
A recent article in Semiconductor Engineering announced The Return of Biasing (read the whole thing here). It’s back because of the quest to build more powerful mobile devices that support long battery life. And with FD-SOI designers can once again easily use what is essentially an old design trick for controlling threshhold voltage (Vt). (In the simplest terms, Vt is the point at which a transistor turns on or off.)
This piece is a really good read if you want to know why body biasing is back in the game, and when and how it’s used. It gets fairly technical, but it’s also very clear. SemiEngineering’s Ann Steffora Mutschler really explores the advantages and issues in interviews with experts at ARM and ST, among others. They explained, for example, the differences between leveraging body biasing on bulk and FD-SOI.
By way of background, btw, for much of the history of chip design, body biasing was standard operating procedure. But, as ST Marketing Director Giorgio Cesana noted, body biasing effectively ended at the 40nm node for bulk, and is unworkable in FinFETs. But with FD-SOI, you can not only lower the Vt, but greatly expand the Vdd (supply voltage) range.
ARM Fellow Rob Aitken notes that, “If you are using an FD-SOI type of process, then biasing the substrate is fairly straightforward because the insulator is just sitting there. There are some mechanics to doing it, but the process is tuned to do it easily.”
You really will want to read the whole piece to get a fuller understanding of why and how the use of body biasing is once again on the rise.
Before summer’s no more than a twinkle in our eyes, let’s take a moment to catch up on a key event where FD-SOI took center stage: Leti Innovation Days. French research powerhouse Leti was celebrating 50 years of innovation, so it was a real gala event.
FD-SOI and other SOI technologies were seen and heard throughout the presentations and in the exhibition spaces. But there were a couple of things that were especially interesting that I’ll cover here in ASN. In particular, a panel discussion with GF, Synopsys and Qualcomm; and the big announcement from Leti and Fraunhofer supporting continued FD-SOI development.
(There were also some great info about body biasing in FD-SOI, but we’ll save that for a future post.)
The Panel & More
A session on Micro-nano Pathfinding and the Digital Revolution featured a fascinating panel discussion on Future Applications and New Technologies. As Rajesh Pankaj from Qualcomm, Alain Mutricy from GF and Antun Domic from Synopsys discussed the prospects, FD-SOI quickly took center stage.
Here are some FD-SOI observations from GF’s Alain Mutricy:
It’s planar, so it’s not hard to design in.
It’s the only technology that can get down to 0.4V, and it has the lowest leakage/cell. That will be key for all mainstream applications (except high-end servers) for at least a decade or two.
12 FDX with forward body bias (FBB) will get 7nm FinFET performance.
They’re looking forward to broad FD-SOI adoption. It will enable the next wave of technology and mobile devices.
Synopsys’ Antun Domic noted that:
Currently, 50% of silicon area comes from just 3 or 4% of designs. FD-SOI makes design simpler, so the EDA companies are looking for it to open the door to more designs.
From a design perspective, three thresholds was standard, but that’s not enough. Place and route could stretch to 10 or 15 corners. FD-SOI simplifies tool flow and cuts mask costs. It’s less complicated than you think.
That tech session, btw, began with an excellent testimonial by Leti partner, Soitec. (Remember: the technological innovation that enabled modern SOI wafers came out of Leti and was industrialized by Soitec.) Check out the snapshot below to get an idea of all the areas that SOI-based technologies address.
Leti, Fraunhofer & FD-SOI
The big piece of news to come out of Leti Days is that Leti is teaming up with Fraunhofer to “…strengthen microelectronics innovation in France and Germany” (read the press release here). The agreement was signed by Leti CEO Marie Semeria and Fraunhofer Group for Microelectronics Chairman Hubert Lakner at an official ceremony. A lively the press conference followed. Prof. Lakner emphasized that they are working on a common European roadmap, with a clear plan for collaboration on FD-SOI. Europe, he said, is a good idea, and working together, France and Germany can do a lot for industry. For FD-SOI, Leti is focused on the front-end, and Fraunhofer is working on the back-end.
Working together, they can elevate pillars like FD-SOI from the country level to the European level, noted Dr. Semeria. And that puts them in a more elevated position for EC funding initiatives such as an upcoming IPCEI – which stands for Important Project of Common European Interest.
Initially, however, the focus will be on extending CMOS and More-than-Moore technologies to enable next-generation components for applications in IoT, augmented reality, automotive, health, aeronautics and other sectors, as well as systems to support French and German industries. A second phase extending to other partners and countries is possible. We’ll keep you posted.
In closing, I’m sure you’ll all join me in extending hearty congratulations to Leti on their 50th anniversary. And here’s to their next 50 years of innovation – can you imagine what that might bring? It rather boggles the mind, doesn’t it?
This is the second part of ASN coverage of Day 2 of the recent SOI Workshop in Tokyo, which was dedicated to the “Convergence of IoT, Automotive through Connectivity”. Many of the presentations are now posted and freely available – click here to see the full list.
Peter Rabbeni, GlobalFoundries’ Sr. Director of 5G BizDev and Product Line Marketing focused on mmWave and why/how 5G. In his talk, Delivering on the Promise of 5G: Semiconductor Solutions for the Next Wave of Data, he pointed out that there’s not one solution for all use cases – but there is an SOI solution for all the opportunities.
You need mmWave for latency, simultaneous connectivity, energy-efficiency and mobility, he explained. mmWave addresses the trade-off between distance and data rates. In a phase array, the beam is steered, but because of atmospheric absorption, you have to do multiple beams at high frequencies.
RF-SOI technology is already found in virtually every smartphone in the world. Now, he sees two main benefits in RF-SOI (a partially depleted technology that uses “trap-rich” substrates, btw) in the move to 5G and mmWave. One is device stacking, which you can do in SOI to overcome the Johnson Limit (a tradeoff between breakdown voltage and frequency). The other comes from the benefits inherent in the substrate: high-resistivity, high-Q and isolation. It means you can have smaller arrays for each element, and fewer chips per array. That’s key: you need those smaller arrays for handsets and customer premises equipment.
Different designers are taking different approaches to RF, he notes. There are those doing FEM-centric designs, which integrate from the antenna back toward the transceiver. And then there are those that are doing integration-centric designs, which target integration from the transceiver/BB toward the antenna. The first approach is being driven by those customers with unique IP and presence in the front-end module space. The other is being driven by folks with IP and presence in the SOC space. Both will exist in some form, he contends. 45RFSOI is well aligned with the first case and focused primarily with FEM leadership performance and integration. 22FDX, on the other hand, is very well suited for transceiver/baseband ADC/DAC integration and can integrate the FEM functionality as well. Pathfinding on the FEM integration component is on-going for 22FDX.
SOI is “…the perfect solution to our needs”, said Steven Yeung, Design Manager with MIPS/Imagination Technologies in his talk, MIPS Leading Heterogenous Compute in Automotive & IP. The cost of failure is increasing he noted, citing the ISO standard 26262 for functional safety in road vehicles, and SOI “helps a lot”.
As noted in the presentation title, research powerhouse Leti sees that the Future of the Automotive Industry is Paved With SOI. Vincent Roger of Leti’s Corporate Business Development made convincing arguments as to why FD-SOI is the right solution for automotive:
you need advanced digital circuitry for all computational tasks in the automotive environment
the 3-generation node gap between automotive and consumer is closing
FD-SOI is more power efficient than planar bulk (both at 28 and 22nm) or FinFET (16nm)
it’s simpler in terms of design and IP portability than FinFET
it’s a proven solution, with better reliability and lower design costs
it addresses all performance levels and communications
it simplifies integration of control electronics for distributed sensors
Leti is actively working on getting RF capabilities in FD-SOI adopted more quickly. For example, they are developing RF models for their UTSOI-2 modeling suite for FDSOI, including back bias effects. And they’re also developing innovative basic design blocks that prove the technology validity and add new functionality.
He also sees an even bigger role for RF-SOI, the technology of choice for RF Front End Modules for connected vehicles and 5G applications. With Soitec, they’re working to keep improving existing substrates and introduce new concepts.
SOI wafer suppliers (Soitec, SEH and Simgui) are expanding capacity, said Soitec EVP Thomas Pilisczcuk. His talk, The Role of Substrates in Accelerating Mass Adoption of SOI Technologies, reviewed the various SOI substrates and partners across FD-SOI, RF-SOI, photonics, power, image sensors and more.
Soitec is launching a program called FIRST (for First Integration Ramp of SOI Toolbox) to help customers reach competitive yields fast. They are also help customers facilitate SOI integration into design and manufacturing.
There are still more talks that are now posted on the SOI Consortium website. IHS/Markit made a very interesting high-level presentation on LIDARs & Sensor Fusion ECUs Advancing ADAS Architectures Toward Automated Driving, which called for chipmakers to integrate more features. Nokia Future X Network for 5G & IoT looked at infrastructure (they use their own chipsets). ST looked at smart cities in Sensor-to-Cloud Connectivity for IoT.
Equipment makers are also eager participants in the FD-SOI ecosystem. Screen’s presentation was entitled Full Participation Within the SOI Consortium. The Applied Materials talk, Enabling SOI and IoT: An Equipment and Materials Engineering Perspective, covered how they’re working with their customers and their customers’ customers to understand the trends and enable the device roadmap.
Mark your calendars: the next workshop sponsored by the SOI Consortium will be in Shanghai this September 26th and 27th (one day is all about FD-SOI, the other about RF-SOI). You can now register or ask for an invitation: see Events on the SOI Consortium website. Last year’s Shanghai event was really dynamic and absolutely packed, so you’ll want to make sure you register early. (But if you can’t make it, you can of course read about later it in ASN!)
Leveraging GF’s 22FDX® FD-SOI technology, GlobalFoundries and Verisilicon are developing IP to enable a complete cellular modem module on a single chip, including integrated baseband, power management, RF radio and front-end module combining both Narrowband IoT (NB-IoT) and LTE-M capabilities. (Read the full press release here.) The new approach is expected to deliver significant improvements in power, area, and cost compared to current offerings.
The companies say this will be the industry’s first single-chip IoT solution for next-generation Low Power Wide Area (LPWA) networks. LPWA technology takes advantage of the existing LTE spectrum and mobile infrastructure, but focuses on delivering ultra-low power, extended range, and much lower data rates for devices that transmit small amounts of infrequent data, such as connected water and gas meters.
The two leading LPWA connectivity standards are LTE-M, which is expected to get traction in the U.S. market, and NB-IoT, which is gaining ground in Europe and Asia. For example, the Chinese government has targeted NB-IoT for nationwide deployment over the coming year. The combination of these two technologies is expected to push cellular M2M module shipments to nearly half a billion by 2021, according to ABI Research.
“Integrated with RF and PA on GF 22FDX, the baseband and protocol stack are being implemented on our energy efficient and programmable ZSPnano that is optimized for control and data flow with powerful low latency, single cycle instructions for signal processing,” said Wayne Dai, VeriSilicon Chairman, President and CEO. “GF’s new 300 mm fab for FDX in Chengdu and IP platforms such as this single chip solution for integrated NB-IoT and LTE-M, will have significant impact on China IoT and AIoT (AI of Things) industries.”
GF and VeriSilicon expect to tape out a test chip based on the integrated solution, with silicon validation in Q4 2017. The companies plan to pursue carrier certification in mid-2018.