Tag Archive IP

Semiwiki Bloggers Creating FD-SOI Buzz

Bloggers for the mega Semiwiki site are warming fast to FD-SOI.  Three recent pieces have generated a lot of good comments and discussions – check them out here (links embedded):

IP Value Starts at the Substrate Level

If you say “IP” in the chip business, everyone thinks of cores and design. But in fact, the importance of intellectual property for chips can extend right down to the substrate level.

Engineered, advanced wafer substrates open new doors for designers. For example, Soitec recently announcement that we are licensing some of our Smart Stacking™ generic bonding IP related to back-side illumination (BSI)  in image sensors to TSMC. This is a clear testament to the value of IP starting at the substrate level. But in fact, TSMC is not the first company licensing our portfolio for BSI: ST took a license for BSI a few years ago.

Soitec is known throughout the industry for our Smart CutTM technology, the enabler of the silicon-on-insulator (SOI) wafer revolution. Most of today’s industry-leading SOI wafers destined for chip manufacturing are made by wafer suppliers using the Smart Cut layer transfer technology. The Smart Cut technology is also behind the development of new families of standard and custom engineered wafers.

In fact, Soitec’s IP portfolio extends to over 3000 patents covering over 600 inventions, and every year, we add about 350 more patents.  This gives us what is arguably the most complete advanced substrate engineering portfolio in the world.


So when speaking of Soitec’s expertise, we might think first of SOI wafers, but in fact, such IP is generic. It can be used as building blocks in leading-edge microelectronic products, applied to an array of materials covering a wide realm of applications.

For example, Smart Cut™ technology is now being leveraged by Sumitomo Electric to produce GaN substrates for high-performance LED lighting applications. Following the announcement of last year, Sumitomo is now industrializing the product and investing in Smart Cut technology.

In the case of Soitec’s Smart Stacking™ generic bonding technology, one of the earliest applications was indeed BSI image sensors, to help manufacturers to deliver increased sensitivity and smaller pixel size. But Smart Stacking will also be leveraged to dramatically improve the performance of RF products, opening new doors to future RF and 3D-integration applications.

One example of how effective our IP policy is came about in 1997 when we contracted with  Shin-Etsu Handotai Co., Ltd (SEH) of Japan for SOI manufacturing using our Smart Cut technology. The manufacturing agreement helped establish SOI products made with Smart Cut technology as the global standard.

Last year, Soitec and SEH (which is the world leader in the manufacturing of silicon wafers) announced a Smart Cut™ licensing extension and expanded technology cooperation agreement. The new partnership includes an extended 10-year licensing agreement between the two companies and establishes a new level of joint technology cooperation. It will facilitate the development and wafer supply of SOI wafers to meet major market opportunities such as SOI for RF devices, FinFETs on SOI and FD-SOI.

The agreement expands the scope of the partnership between Soitec and SEH, including cross-licensing Smart Cut related patents between the two companies. SEH will now also be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), thereby further expanding the scope of applications.

Soitec’s expertise also extends to the domain of III-V epitaxy, which is leveraged in substrates for applications like RF, power, and lighting.

Beyond microelectronics, we are leveraging and expanding our innovation portfolio in energy markets. For example, earlier this year we announced the industry’s first four-junction solar cell for concentrator photovoltaic systems. We leverage both our proprietary semiconductor-bonding (Smart Stacking™) and layer-transfer (Smart Cut™) technologies to successfully stack non-lattice-matched materials while also raising the possibility of re-using expensive materials. These cells have recently reached efficiency of 44.7%, setting the world record.

The Soitec IP portfolio now represents over 20 years of successful innovation at the substrate level.   We invest around 10% of our revenue in R&D to develop and perfect breakthrough materials technologies. Our R&D teams work closely with manufacturers, as well as with laboratories such as CEA-Leti and the Fraunhofer Institute for Solar Energy Systems. We also take full advantage of the high-tech resources available in and around all of our locations worldwide.

In short, the innovations found in our substrate engineering IP portfolio are at the heart of how we lead, grow and maximize value through incremental and breakthrough solutions for the electronics and energy industries.

Soitec has licensed some of its intellectual property portfolio related to back-side illumination technology for image sensors to TSMC

Soitec, a world leader in generating and manufacturing revolutionary semiconductor materials for the electronics and energy industries, has licensed some of its intellectual property (IP) portfolio related to back-side illumination (BSI) technology for image sensors to TSMC. BSI is a key enabling technology in the race to develop small-pixel, high-quality image sensors used in consumer products such as digital cameras, smart phones and other portable electronics.  In this case, the BSI technology uses some of the key process steps of Soitec’s Smart Stacking™ generic technology.

The company also announced that it has received ISO 22301:2012 certification for its Bernin site (near Grenoble, in South-East France). This international standard provides a framework for companies in implementing procedures that will ensure the continuity of their critical businesses during exceptional circumstances. Soitec, the first ISO 22301:2012 certified company in France, has thus received recognition for the quality of its business continuity management system to protect the company from disruptive incidents (fires, unavailability of its information system, pandemics, malicious acts, etc.) by reducing their potential impact on its business.

In solar news, Soitec announced its newest concentrated photovoltaic (CPV) module featuring a record power-generating efficiency of 31.8 percent. The new module, which is already in industrial volume production, has the highest efficiency of any commercial product available for multi-megawatt installations.

Fully-Depleted SOI Workshop Follows VLSI in Kyoto

The SOI Consortium’s FD-SOI Workshop is returning to Japan. This time it follows on the heels of the big 2013 Symposia on VLSI Technology and Circuits in Kyoto.

The VLSI Symposia run from June 10-14; the SOI Consortium’s workshop on fully-depleted SOI technologies follows on Saturday, June 15, at the Kyoto Research Park. The Consortium event will run from 3 p.m. to 5:30 p.m., just after the Japan Society for the Promotion of Science (JSPS) Symposium on low-voltage devices and circuits (which is being held during the same week as the VLSI Symposia).

Registration for the FD-SOI Workshop is free and open to everyone — click here to access the registration website.


These are always lively, well-attended events. Here’s what the Consortium has lined up for the Kyoto workshop.

The 28nm FD-SOI technology offer:

  • 28nm FD-SOI Industrial Solution: Overview of Silicon-Proven Key Benefits – Laurent Le Pailleur, Technology Line Management Director, STMicroelectronics
  • SoC Differentiation using FD-SOI – A Manufacturing Partner’s Perspective – Shigeru Shimauchi, Japan General Manager, GlobalFoundries
  • Ultra Thin Body and Buried Oxide Substrate Supply Chain – Nobuhiko Noto, Deputy General Manager – Advanced Wafers Dept. – Technology & Development, SEH

Design methodologies:

  • Architectural Choices and Design Implementation Methodologies for Exploiting Extended FD-SOI DVFS and Body Bias Capabilities (short course) – David Jacquet, Sr. Principal Engineer, Design & Architecture for Energy Efficiency CPU & GPU Subsystem, STMicroelectronics
  • SoC Design for FD-SOI – Dr. Wayne Dai, CEO, VeriSilicon

Advances in Technology Development:

  • Advances and Silicon Results on 14nm planar FD-SOI Technology – Carlo Reita, CMOS Components Program Manager, CEA-Leti
  • Elements for the Next Generation FinFET CMOS Technology – Terence Hook, Sr. Technical Staff Member, IBM Semiconductor R&D Center (he also wrote an extremely popular ASN article on FinFETs on SOI recently – click here if you missed it)

The organizers for this event are:

  • Horacio Mendez
Executive Director, SOI Industry Consortium
  • Philippe Magarshack
Executive VP, Design Enablement and Services, Digital Sector, STMicroelectronics
  • Joel Hartmann
Executive VP, FE Manufacturing and Process R&D, Digital Sector, STMicroelectronics
  • Mike Noonen
Executive VP, Global Sales, Marketing, Design & Quality, GlobalFoundries

BTW, the presentations from the last SOI Consortium Workshop (April ’13 in Taiwan) are now available on the Consortium website. They’re all really excellent – for example: SoC Differentiation using FDSOI – A Manufacturing Partner’s Perspective, by Subramani Kengeri of GlobalFoundries is packed with side-by-side bulk vs. FD-SOI data.

Next up at ASN, we’ll flag the big SOI-based papers to watch for at VLSI (and there are some knock-your-socks-off results!).

Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant from the Technology Strategy Board SMART

Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant (about 292K Euros or $380.5K) from the Technology Strategy Board SMART. Working with the major foundries developing FD-SOI and FinFET technologies, the grant will be used in the development of a demonstrator chip to showcase sureCore’s patented array control and sensing scheme, which significantly lowers active power consumption. Through a combination of detailed analysis and using advanced statistical models, sureCore has designed an SRAM memory consuming less than half the power of existing solutions. SureCore is working closely with Gold Standard Simulations (GSS) Ltd. (GSS Founder/CEO Asen Asenov is a sureCore director).

GF’s Two Flavors of FD-SOI – Kengeri Explains (Exclusive ASN Q&A)

Subramani Kengeri

Subi Kengeri, Vice President of Advanced Technology Architecture, GlobalFoundries

Hearing the news that GlobalFoundries would be offering two flavors of FD-SOI, ASN asked the company to explain the strategy further. Here are the responses provided by Subi Kengeri, Vice President of Advanced Technology Architecture.

What do you see as the FD-SOI benefits for chip designers?

  • Lower SRAM Vmin for retention and lower operating Vmin for Logic
  • Wider range of Voltage operation for performance/power trade-off
  • Total dielectric isolation equates to lower capacitances, lower leakage, and latch-up immunity
  • Ultra-thin silicon film provides excellent electrostatic control and optimum transistor performance
  • Back-bias control gives an additional speed boost
  • Simple planar process using same front end and back end as our 28SLP process, which means fewer process steps and fewer masks, helping to absorb the additional substrate cost

What are your plans for making FD-SOI available to your customers?

We are the manufacturing partner for ST’s FD-SOI technology. We also are planning to offer the technology to other customers who may be interested, but we have not announced details yet. We are the only pure-play foundry with deep experience in both bulk and SOI technologies, which allows us to offer a broader range of technologies at advanced nodes.

GlobalFoundries' Fab

GlobalFoundries’ Fab 8 in upstate NY

Can you elaborate on the “maximum” version of FD-SOI — tuned for specific applications — what sorts of things would those be?

Examples of features in the Maximum version of FD-SOI:
a. Back-bias capability on logic for higher performance
b. Denser SRAM by taking advantage of lesser variability of Fully depleted device
c. Base Vts tuned for specific applications (performance vs power trade-off)

And the “minimum” version — a simple and “out of the box” FD-SOI technology — who/what is this for?

a. No Back-bias supported
b. All SRAMs are foot-print compatible to 28SLP
c. Fully depleted device offers better Vmin and power advantages: Optimized for Mobile Applications

Are there any special logistics in terms of the PDK, IP, etc?

a. PDKs are similar to bulk CMOS, except the models will support a 4-terminal device for Back-bias
b. In the base version (termed as minimum version above), IP’s Physicals are fully compatible with bulk CMOS, but would require electrical re-characterization to take advantage of improved FD-SOI device characteristics
c. In the extended version (termed maximum version above), IPs will be designed to take advantage of Back-bias for better performance/power trade-offs in specific applications

What is the next node, and when will that roll out?

See slide 8 of [this] presentation:

Slide8 - Planar 28nm FD-SOI Technology

Considerations for Bulk CMOS to FD-SOI Design Porting – Key Excerpts

The latest white paper from SOI Consortium members is loaded with technical information. The full paper is available on the website. Here are some of the highlights.

In approaching a bulk-to-FD-SOI port, different perspectives can be taken:

  • IP Porting: The focus may be to easily port the libraries and other IP available in Bulk to FD-SOI, accepting some redesign work at System-On-Chip (SOC) integration level.
  • Full chip design porting: Alternatively, it may be important to assess the efforts needed to start from an existing SOC design on Bulk and port this full chip to FD-SOI.

Key messages

The efforts required to port a design will depend on the exact foundry offering and associated Design Kit. Nevertheless, in essence:

  • Designing for planar FD-SOI technology is the same as designing for planar bulk CMOS.
  • IP Porting from Bulk to FD-SOI (same node, same foundry) can be very direct, for worthwhile benefits at fast time-to-market – with some more work for Analog IP.
  • Further optimization efforts can bring even greater product differentiation.
  • SOC Porting from Bulk to FD-SOI can be very direct – and appropriate technology choices by the foundry (for example VT offering) shall facilitate this.
  • FD-SOI offers efficient knobs to further optimize SOC performance.

Circuit-Level Benefits

FD-SOI transistors, because of their ultra-thin body, have a much closer-to-ideal behavior than classical planar bulk CMOS. For designers this translates to unique advantages at the circuit level, including:

  • Faster operation at equivalent leakage, with the relative performance gap growing tremendously in the low Vdd range,
  • Or, conversely, the ability to reach the same target frequency at significantly lower Vdd, enabling large power savings,
  • Drastically reduced variability, with a positive impact on VDDmin of SRAM arrays, chip-level leakage, etc.
  • Enhanced efficiency of low-power design techniques such as DVFS (Dynamic Voltage and Frequency Scaling), back-bias, etc.

Standard Cells

Direct porting is an option for seeing worthwhile benefits with the fastest time-to-market. It involves swapping bulk transistors for FD-SOI transistors at constant cell layout and re-characterizing the cells.

Alternatively, if ultimate performance is sought, re-optimization of selected cells vs. exact transistor characteristics may further improve the results. The exact return on efforts would be confirmed by checking the specifications of the FD-SOI technology offered by the foundry.


With FD-SOI on ultra-thin Buried Oxide (BOx), the substrate underneath the BOx is normally tied to Vdd or Gnd. This is not disruptive for the design and is handled by substrate ties exactly in the same way as well biasing in classical bulk CMOS technology; only now the contact to the substrate is made through the BOx.

Then there is the option to have “active” back-bias, to shift the VT or, equivalently, the Ion/Ioff operating point – by shifting the voltage applied under the BOx. In particular, dynamic back-biasing is an extremely efficient technique to either boost performance or cut leakage according to the workload. It is more efficient and usable than the similar body-bias technique on bulk, due to a very good body factor plus the ability to push significantly further the bias voltage without unacceptable leakage. The bias voltage is applied under the BOx using the same substrate tie cells as above, placed in the chip layout every so many microns (PDK-dependent), like bulk substrate ties.

Memory Compilers

For easy porting, the bitcells provided in the FD-SOI PDK should have the same abstract (footprint) as those provided with the bulk CMOS PDK.

Then existing compilers can be re-used, with updated characterization (timing, power, etc.). For the periphery, options are the same as for standard cells: direct port for fastest time-to-market or re-optimization for ultimate performance.

I/Os and Analog

Integration of thick gate-oxide transistors on FD-SOI is not an issue. Non-FET devices will have a counterpart in the FD-SOI device menu. Some of them may actually be provided as Bulk devices, through Bulk-FD-SOI co-integration (by locally etching off the top silicon and BOx to give access to the underlying Bulk substrate). In some cases and depending on foundry choices, there might be a few devices used in the original Bulk design that have no direct counterpart in the FD-SOI-compatible device menu: then it would be necessary to adapt the IP design to come up with a solution based on replacement devices.


SOC porting strategy and design flow

SOC porting strategy and design flow

Straight SOC Porting: wherein the least possible e ort is required (that is, where the ideal case would be reusing the GDS as is).

SOC porting strategy and design flow

Re-optimized SOC implementation: wherein the design team is prepared to invest in a little more speci c design to enjoy further bene ts of the FD-SOI technology (for example, by introducing dynamic back-bias in a SOC that did not use any).

What’s New

Focus ’09: Power Savings & IP

The joint survey we did with the GSA last year clearly indicated that lowering power is a primary driver for designers considering SOI-based solutions. Therefore, our 2009 focus is putting a particular emphasis on IP and outreach efforts highlighting the green, energy-saving advantages of SOI.

Our dedicated IP committee is working hard to close the remaining IP gaps. Concurrently, various members are collaborating to demonstrate the performance of key IP on SOI and solidify the ecosystem around the foundries. Read More

45nm SOI

The Foundry Offering. The IP. The Collaboration.
> It’s All Here

IBM Announces the Industry’s First 45nm SOI Foundry Offering.

logo_IBM_285 IBM’s new 45nm SOI foundry offering is designed to meet the demands of emerging high-performance, low-power markets. The new offering adds ARM’s industry-standard design tools and libraries to the intellectual property (IP) already available through IBM’s existing SOI development infrastructure, allowing a wide range of client designs to take advantage of SOI’s benefits.

IBM testing has shown the potential for 45nm SOI to offer up to 30 percent performance improvement or 40 percent power reduction when compared to bulk technology. IBM expects that price/performance leadership combined with ever- increasing application workload demands will create opportunities for SOI to expand into an even broader range of consumer electronics, such as digital televisions and high-end mobile applications.

“45nm is our 6th generation of SOI technology and is a key driver in many collaborative designs with clients – including networking, storage, gaming and other consumer applications. This foundry announcement is a progression of this deep experience, providing a world-class resource for the industry to build on this proven, next-generation technology.”

Mark Ireland, Vice President,
IBM Semiconductor Platforms

ARM Announces Industry’s First SOI Physical IP Library For IBM’s New 45nm SOI Foundry.

logo_ARM ARM’s SOI physical IP library includes standard cell, memory and I/O libraries for IBM’s fully enabled 45nm SOI foundry. It promises to significantly ease implementation of SOI technology and bring the benefits to a much wider range of semiconductor companies. The ARM SOI physical IP library is supported by standard synthesis and place and route implementation flows that enable customers to quickly implement products without changing design methodologies or training of employees. It supports EDA views for Synopsys, Cadence and Magma tools. Customers can start downloading it free from the ARM Web site now.


“These announcements will continue to proliferate the adoption of SOI technology beyond the traditional high-end segment.”

Horacio Mendez, Executive Director,
SOI Industry Consortium

logo_Semico_195“With these announcements, ARM and IBM have taken the first step toward breaking down major barriers and making SOI a viable alternative for many more applications in networking, storage, communication and consumer applications.“

Joanne Itow, Managing Director,
Semico Research Corp.


“Two years ago, Soitec and ARM announced a joint agreement supporting the development of SOI libraries for the fabless and foundry arenas, promising designers a solution to accelerate SOI adoption and design. The ARM & IBM announcements mark a significant milestone in delivering on our promise.“

André-Jacques Auberton-Hervé, President and CEO,