Bloggers for the mega Semiwiki site are warming fast to FD-SOI. Three recent pieces have generated a lot of good comments and discussions – check them out here (links embedded):
If you say “IP” in the chip business, everyone thinks of cores and design. But in fact, the importance of intellectual property for chips can extend right down to the substrate level.
Engineered, advanced wafer substrates open new doors for designers. For example, Soitec recently announcement that we are licensing some of our Smart Stacking™ generic bonding IP related to back-side illumination (BSI) in image sensors to TSMC. This is a clear testament to the value of IP starting at the substrate level. But in fact, TSMC is not the first company licensing our portfolio for BSI: ST took a license for BSI a few years ago.
Soitec is known throughout the industry for our Smart CutTM technology, the enabler of the silicon-on-insulator (SOI) wafer revolution. Most of today’s industry-leading SOI wafers destined for chip manufacturing are made by wafer suppliers using the Smart Cut layer transfer technology. The Smart Cut technology is also behind the development of new families of standard and custom engineered wafers.
In fact, Soitec’s IP portfolio extends to over 3000 patents covering over 600 inventions, and every year, we add about 350 more patents. This gives us what is arguably the most complete advanced substrate engineering portfolio in the world.
So when speaking of Soitec’s expertise, we might think first of SOI wafers, but in fact, such IP is generic. It can be used as building blocks in leading-edge microelectronic products, applied to an array of materials covering a wide realm of applications.
For example, Smart Cut™ technology is now being leveraged by Sumitomo Electric to produce GaN substrates for high-performance LED lighting applications. Following the announcement of last year, Sumitomo is now industrializing the product and investing in Smart Cut technology.
In the case of Soitec’s Smart Stacking™ generic bonding technology, one of the earliest applications was indeed BSI image sensors, to help manufacturers to deliver increased sensitivity and smaller pixel size. But Smart Stacking will also be leveraged to dramatically improve the performance of RF products, opening new doors to future RF and 3D-integration applications.
One example of how effective our IP policy is came about in 1997 when we contracted with Shin-Etsu Handotai Co., Ltd (SEH) of Japan for SOI manufacturing using our Smart Cut technology. The manufacturing agreement helped establish SOI products made with Smart Cut technology as the global standard.
Last year, Soitec and SEH (which is the world leader in the manufacturing of silicon wafers) announced a Smart Cut™ licensing extension and expanded technology cooperation agreement. The new partnership includes an extended 10-year licensing agreement between the two companies and establishes a new level of joint technology cooperation. It will facilitate the development and wafer supply of SOI wafers to meet major market opportunities such as SOI for RF devices, FinFETs on SOI and FD-SOI.
The agreement expands the scope of the partnership between Soitec and SEH, including cross-licensing Smart Cut related patents between the two companies. SEH will now also be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), thereby further expanding the scope of applications.
Soitec’s expertise also extends to the domain of III-V epitaxy, which is leveraged in substrates for applications like RF, power, and lighting.
Beyond microelectronics, we are leveraging and expanding our innovation portfolio in energy markets. For example, earlier this year we announced the industry’s first four-junction solar cell for concentrator photovoltaic systems. We leverage both our proprietary semiconductor-bonding (Smart Stacking™) and layer-transfer (Smart Cut™) technologies to successfully stack non-lattice-matched materials while also raising the possibility of re-using expensive materials. These cells have recently reached efficiency of 44.7%, setting the world record.
The Soitec IP portfolio now represents over 20 years of successful innovation at the substrate level. We invest around 10% of our revenue in R&D to develop and perfect breakthrough materials technologies. Our R&D teams work closely with manufacturers, as well as with laboratories such as CEA-Leti and the Fraunhofer Institute for Solar Energy Systems. We also take full advantage of the high-tech resources available in and around all of our locations worldwide.
In short, the innovations found in our substrate engineering IP portfolio are at the heart of how we lead, grow and maximize value through incremental and breakthrough solutions for the electronics and energy industries.
The VLSI Symposia run from June 10-14; the SOI Consortium’s workshop on fully-depleted SOI technologies follows on Saturday, June 15, at the Kyoto Research Park. The Consortium event will run from 3 p.m. to 5:30 p.m., just after the Japan Society for the Promotion of Science (JSPS) Symposium on low-voltage devices and circuits (which is being held during the same week as the VLSI Symposia).
Registration for the FD-SOI Workshop is free and open to everyone — click here to access the registration website.
These are always lively, well-attended events. Here’s what the Consortium has lined up for the Kyoto workshop.
The 28nm FD-SOI technology offer:
Advances in Technology Development:
The organizers for this event are:
BTW, the presentations from the last SOI Consortium Workshop (April ’13 in Taiwan) are now available on the Consortium website. They’re all really excellent – for example: SoC Differentiation using FDSOI – A Manufacturing Partner’s Perspective, by Subramani Kengeri of GlobalFoundries is packed with side-by-side bulk vs. FD-SOI data.
Next up at ASN, we’ll flag the big SOI-based papers to watch for at VLSI (and there are some knock-your-socks-off results!).
Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant (about 292K Euros or $380.5K) from the Technology Strategy Board SMART. Working with the major foundries developing FD-SOI and FinFET technologies, the grant will be used in the development of a demonstrator chip to showcase sureCore’s patented array control and sensing scheme, which significantly lowers active power consumption. Through a combination of detailed analysis and using advanced statistical models, sureCore has designed an SRAM memory consuming less than half the power of existing solutions. SureCore is working closely with Gold Standard Simulations (GSS) Ltd. (GSS Founder/CEO Asen Asenov is a sureCore director).
The latest white paper from SOI Consortium members is loaded with technical information. The full paper is available on the website. Here are some of the highlights.
In approaching a bulk-to-FD-SOI port, different perspectives can be taken:
The efforts required to port a design will depend on the exact foundry offering and associated Design Kit. Nevertheless, in essence:
FD-SOI transistors, because of their ultra-thin body, have a much closer-to-ideal behavior than classical planar bulk CMOS. For designers this translates to unique advantages at the circuit level, including:
Direct porting is an option for seeing worthwhile benefits with the fastest time-to-market. It involves swapping bulk transistors for FD-SOI transistors at constant cell layout and re-characterizing the cells.
Alternatively, if ultimate performance is sought, re-optimization of selected cells vs. exact transistor characteristics may further improve the results. The exact return on efforts would be confirmed by checking the specifications of the FD-SOI technology offered by the foundry.
With FD-SOI on ultra-thin Buried Oxide (BOx), the substrate underneath the BOx is normally tied to Vdd or Gnd. This is not disruptive for the design and is handled by substrate ties exactly in the same way as well biasing in classical bulk CMOS technology; only now the contact to the substrate is made through the BOx.
Then there is the option to have “active” back-bias, to shift the VT or, equivalently, the Ion/Ioff operating point – by shifting the voltage applied under the BOx. In particular, dynamic back-biasing is an extremely efficient technique to either boost performance or cut leakage according to the workload. It is more efficient and usable than the similar body-bias technique on bulk, due to a very good body factor plus the ability to push significantly further the bias voltage without unacceptable leakage. The bias voltage is applied under the BOx using the same substrate tie cells as above, placed in the chip layout every so many microns (PDK-dependent), like bulk substrate ties.
For easy porting, the bitcells provided in the FD-SOI PDK should have the same abstract (footprint) as those provided with the bulk CMOS PDK.
Then existing compilers can be re-used, with updated characterization (timing, power, etc.). For the periphery, options are the same as for standard cells: direct port for fastest time-to-market or re-optimization for ultimate performance.
Integration of thick gate-oxide transistors on FD-SOI is not an issue. Non-FET devices will have a counterpart in the FD-SOI device menu. Some of them may actually be provided as Bulk devices, through Bulk-FD-SOI co-integration (by locally etching off the top silicon and BOx to give access to the underlying Bulk substrate). In some cases and depending on foundry choices, there might be a few devices used in the original Bulk design that have no direct counterpart in the FD-SOI-compatible device menu: then it would be necessary to adapt the IP design to come up with a solution based on replacement devices.
SOC porting strategy and design flow
The joint survey we did with the GSA last year clearly indicated that lowering power is a primary driver for designers considering SOI-based solutions. Therefore, our 2009 focus is putting a particular emphasis on IP and outreach efforts highlighting the green, energy-saving advantages of SOI.
Our dedicated IP committee is working hard to close the remaining IP gaps. Concurrently, various members are collaborating to demonstrate the performance of key IP on SOI and solidify the ecosystem around the foundries. Read More
The Foundry Offering. The IP. The Collaboration.
> It’s All Here
IBM’s new 45nm SOI foundry offering is designed to meet the demands of emerging high-performance, low-power markets. The new offering adds ARM’s industry-standard design tools and libraries to the intellectual property (IP) already available through IBM’s existing SOI development infrastructure, allowing a wide range of client designs to take advantage of SOI’s benefits.
IBM testing has shown the potential for 45nm SOI to offer up to 30 percent performance improvement or 40 percent power reduction when compared to bulk technology. IBM expects that price/performance leadership combined with ever- increasing application workload demands will create opportunities for SOI to expand into an even broader range of consumer electronics, such as digital televisions and high-end mobile applications.
“45nm is our 6th generation of SOI technology and is a key driver in many collaborative designs with clients – including networking, storage, gaming and other consumer applications. This foundry announcement is a progression of this deep experience, providing a world-class resource for the industry to build on this proven, next-generation technology.”
Mark Ireland, Vice President,
IBM Semiconductor Platforms
ARM’s SOI physical IP library includes standard cell, memory and I/O libraries for IBM’s fully enabled 45nm SOI foundry. It promises to significantly ease implementation of SOI technology and bring the benefits to a much wider range of semiconductor companies. The ARM SOI physical IP library is supported by standard synthesis and place and route implementation flows that enable customers to quickly implement products without changing design methodologies or training of employees. It supports EDA views for Synopsys, Cadence and Magma tools. Customers can start downloading it free from the ARM Web site now.
“These announcements will continue to proliferate the adoption of SOI technology beyond the traditional high-end segment.”
Horacio Mendez, Executive Director,
SOI Industry Consortium
“With these announcements, ARM and IBM have taken the first step toward breaking down major barriers and making SOI a viable alternative for many more applications in networking, storage, communication and consumer applications.“
Joanne Itow, Managing Director,
Semico Research Corp.
“Two years ago, Soitec and ARM announced a joint agreement supporting the development of SOI libraries for the fabless and foundry arenas, promising designers a solution to accelerate SOI adoption and design. The ARM & IBM announcements mark a significant milestone in delivering on our promise.“
André-Jacques Auberton-Hervé, President and CEO,