The presentations from the SOI Consortium sponsored workshop held during Semicon West are now posted and freely available on the website – click here to see the full agenda with links to the presentations. The workshop, entitled 4G/5G Connectivity: Opportunities for the SOI Supply Chain, was well-attended and generated excellent discussions.
If you don’t have time to look at all of the ppts, here are quick overviews.
Handel Jones is an industry veteran, China expert and longtime follower of the SOI ecosystem. High performance with low power consumption are the key requirements for the continued growth in the semiconductor industry, he said, making FD-SOI the right choice for a wide range of products. Here’s how he sees it:
He estimates the yearly TAM (total available market) for FD-SOI based products in the range of $46 billion over the next 10 years, largely driven by needs for ultra-low power and RF integration. He goes on to break out volumes by applications (including ISPs – image signal processors; and CIS – CMOS image sensors), foundry markets by feature dimension and to map out technology trends.
Mobile Radio Transformation in the Age of 5G: A Perspective on Opportunities for SOI, Peter Rabbeni, Vice President, Globalfoundries.
Peter Rabbeni is an RF expert par excellence, having overseen the shipping of over 35 billion RF-SOI products to date. In his presentation, he details how 5G NR (New Radio) sub-6GHz frequency band specifications significantly increase frequency range and channel bandwidth, and how new band support and MIMO complexity and die size per handset are driving complexity in RF FEMs. Furthermore, 5G/mmWave phased arrays are driving a paradigm shift in the approaches that can be taken, he explains, so greater integration is needed. Here’s a great slide showing where GF’s two main SOI technologies come into play:
Working in partnership with industry leaders around the world, Leti has been the research powerhouse behind all things SOI since the early 1980s. In fact Reuters ranks them #2 in their most recent list of the World’s Most Innovative Research Institutions. This presentation reviews the key technical benefits of FD-SOI for IoT and IMT (that’s international mobile communications, btw).
This presentation really puts the context around engineered substrates. Here are two excellent and useful slides here that identify which engineered substrates go where in the 5G world, and the engineered substrates that Soitec provides. Check these out:
Ultra-thin Double Layer Metrology with High Lateral Resolution, Bernd Srocka, Vice President, Unity GmbH.
In case you’re not familiar with them, Unity provides a wide range of solutions in metrology and inspection. Both the top silicon layer and BOX layer of wafers for FD-SOI applications have draconian requirements that have required new approaches in metrology to ensure the thickness and homegeneity control of these very thin layers.
Shanghai-based Simgui partners with Soitec, using SmartCut™ technology for the production of RF-SOI wafers. It is doubling its capacity to reach 400K over the next year, and expanding into 300mm. China is aggressively working on 5G and plans to deploy 5G commercialization in 2020. Jeff Wang’s is a terrific presentation detailing the rollout. (BTW, in addition to the massive funding effort underway, the government created the National Silicon Industry Group (NSIG) to support the semiconductor material ecosystem in China. You’ll want to keep up with what’s going on here). Here’s the slide that summarizes the SOI ecosystem in China – the presentation then goes on to detail who does what.
Inspection and Metrology Relevance in SOI Manufacturing, Jijen Vazhaeparambil, Vice President & General Manager, KLA-Tencor.
K-T has played a strategic role in the SOI story going back for decades (and in fact they wrote a piece for the third edition of ASN back in 2005!), ensuring metrology innovations for things that hadn’t previously need detection and measurement. With each new set of requirements, they rose to the occasion with wafer metrology solutions that helped increase quality and decrease costs. This presentation recaps some of them.
By Adele Hars, ASN Editor-in-Chief
Speculation is mounting following ST’s April 28th announcement that they’d signed on a new first-tier foundry for 28nm FD-SOI manufacturing. As of this posting, they haven’t yet said which one it is.
The social media-sphere is abuzz about the mystery foundry – with posters in LinkedIn groups, Twitter, SemiWiki and various industry news sites and forums postulating that it might be Samsung, or UMC, or SMIC or…?
Then David Manners of Electronics Weekly said he’d heard it was SMIC, which launched another round of furious speculation.
But for now, ST’s position is to keep shtum, saying only that we’ll just have to wait to find out which foundry it is until they’re ready to make an official announcement…which caused another round of speculation as to when that would be. Some say they’ll announce at their Investors and Analysts Day on May 15th. Certainly the investment community will press for details, right?
The “we’ve-signed-but-we’re-not-saying-with-whom” news came out of a press release issued with the STMicroelectronics’ 2014 First Quarter Financial Results (read press release here). Jean-Marc Chery, Executive Vice President and General Manager, Embedded Processing Solutions, was quoted as saying, “We have just signed a strategic agreement with a top-tier foundry for 28nm FD-SOI technology. This agreement expands the ecosystem, assures the industry of high-volume production of ST’s FD-SOI based IC solutions for faster, cooler, and simpler devices and strengthens the business and financial prospects of the Embedded Processing Solutions Segment.”
During the follow-up call with analysts (transcript on Seeking Alpha here), CEO Carlo Bozotti added that, “ST’s unique FD-SOI technology is well on its way to become a significant revenue generator for 2015 and beyond….” And the Board of Directors announced that Jean-Marc Chery, who’s been quite a champion of FD-SOI, has been named as ST’s new COO.
Further fanning the flames, in a follow-up piece, Manners quoted KT’s CEO as saying FinFET yields “…are proving to be the most challenging that the industry have ever faced, and even the smallest variation and process margin can cause significant yield losses for these devices.” Now we all know that FinFETs are part of the equation – the question is when and for which apps. But Manners suggested that the current FinFET yield issues are prompting companies to take another look at “simpler, cheaper FD-SOI”.
So we wait with bated breath. Stay tuned – as soon as ST makes an official announcement, you’ll read about it here at ASN.
SOI (especially fully depleted “FD-SOI”) was a hot topic in the video and audio interviews that Debra Vogler of SST released recently.
Here are brief summaries of the most important SOI-related interviews – with top brass from Leti, Soitec, KT, EVG and Qcept – that she made at Semicon West ’11.
(If you need a quick backgrounder on FD-SOI basics, see this explanation from the SOI Industry Consortium.)
Laurent Malier, CEO of Leti – the process technology:
Amir Azordegan, senior director of marketing for Surfscan at KLA-Tencor – the inspection systems:
Paul Lindner, executive technology director, EV Group – wafer bonding systems:
Robert Newcomb, executive VP of operations, Qcept Technologies – advanced defect detection technologies:
KLA-Tencor says its new WaferSight 2 is the industry’s first enabling wafer suppliers and chipmakers to measure bare wafer flatness, shape, edge roll-off and nanotopography in a single metrology system for 45nm and beyond. SOI wafer-supplier Soitec was a beta site.
New in-line inspection equipment from KT reaches new heights in accuracy for sorting out cleanable particles from killer defects.
At the 45nm node, the very nature of the defects and the particularities of the substrate impact light scattering detection methodologies.
KLA-Tencor’s new Surfscan SP2XP system not only captures more shallow defects like stains or residues, it significantly improves the ability to distinguish cleanable particles from killer defects. Read More
Historically, chipmakers conducting incoming quality control (IQC) on SOI wafers used for advanced logic devices are challenged in inspecting these substrates as efficiently and effectively as their bulk counterparts.
The prevailing inspection process utilizes visible light inspection systems. However, these systems often require specific recipe setups and tool calibrations for each SOI wafer type and thickness. This has hampered the ability of chipmakers to establish consistent results at a standard level, and it has also resulted in slower time to results. What chipmakers need in order to accurately and quickly qualify their SOI wafers is a high-throughput capability to inspect SOI substrates, ideally using the same recipe and calibration across multiple wafers. Read More