Tag Archive Microsoft

Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct)

S3Sheader

(For best rates, register by September 18th.)

The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco.

Photo Credit: Catherine Allibert

Photo Credit: Catherine Allibert

Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S conference was successful by any measurement. The first year of the new conference leading-edge experts from 3D Integration, Sub-threshold Microelectronics and SOI fields gathered and we established a world class international venue to present, learn and debate about these exciting topics. The overall participation at the first year of the new conference grew by over 50%, and the overall quality and quantity of the technical content grew even more.

This year we are looking forward to continuing to enhance the content of the 2014 S3S Conference.

 

Short courses: Monolithic 3D & Power-Efficient Chip Tech

On Monday, Oct. 6 we will feature two Short Courses that will run in parallel. Short courses are an educational venue where newcomers can gain overview and generalists can learn more details about new and timely topics.

The short course on Monolithic 3D will be a full day deep dive into the topic of three-dimensional integration wherein the vertical connectivity is compatible with the horizontal connectivity (10,000x better than TSV). Already there are extremely successful examples of monolithic 3D Flash Memory. Looking beyond this initial application, we will explore the application of monolithic 3D to alternate memories like RRAM, CMOS systems with silicon and other channel materials like III V. In addition, a significant portion of the short course will be dedicated to the exciting opportunity of Monolithic 3D in the context of CMOS Logic.

The other short course we will offer this year is entitled Power Efficient Chip Technology. This short course will address several key aspects of power-efficiency including low power transistors and circuits. The course will also review in detail the impact of design and architecture on the energy-efficiency of systems. The short course chairs as well as the instructors are world class leading experts from the most prestigious industry and academic institutions.

 

Conference program

The regular conference sessions will start on Tuesday Oct. 7 with the plenary session, which will feature presentations from Wall Street (Morgan Stanley Investment Banking), Microsoft and MediaTek. After the plenary session we will hear invited talks and this year’s selection of outstanding papers from international researchers from top companies and universities. The most up to date results will be shared. Audience questions and one on one interaction with presenters is encouraged.

Back by popular demand we will have 2 Hot Topics Sessions this year. The first Hot Topic Session is scheduled for Tuesday Oct. 7th and will feature exciting 3DI topics. The other Hot Topics session is scheduled for Thursday Oct 9 and will showcase new and exciting work in the area of MEMS.

Our unique poster session and reception format will have a short presentation by the authors followed by one on one interaction to review details of the poster with the audience, in a friendly atmosphere, around a drink. Last year we had regular posters as well as several invited posters with very high quality content and we anticipate this year’s poster session to be even better than last years.

We are offering a choice of two different fundamentals classes on Wednesday afternoon. One of the Fundamentals classes will focus on Robust Design of Subthreshold Digital and Mixed Circuits, with tutorials by the worlds leading experts in this field. The SOI fundamentals course is focused on RF SOI Technology Fundamentals and Applications.

Our technical content is detailed on our program webpage.

 

Panel discussions, cookout & more

Keeping in line with tradition, on Wednesday night we will have a hearty cook out with delicious food and drink followed by the Panel Session entitled Cost and Benefit of Scaling Beyond 14nm. Panel speakers from financial, semiconductor equipment, technology, and academic research institutions will gather along with the audience to debate this timely topic. Although Thursday is the last day of the conference we will have stimulating presentations on novel devices, energy harvesting, radiation effects along with the MEMS Hot Topic Session and Late News Session. As always we will finish the conference with the award ceremony for the best papers.

SFstreetsignOur conference has a long tradition of attracting presenters and audience members from the most prestigious research, technology and academic institutions from around the world. There are many social events at the S3S Conference as well as quiet time where ideas are discussed and challenged off line and people from various fields can learn more about other fields of interest from leading experts.

The conference also offers many opportunities for networking with people inside and also outside ones area. The venue this year is San Francisco. We chose this location to attract the regions leading experts from Academia and Industry. If you have free time we encourage you to explore San Francisco which is famous for a multitude of cultural and culinary opportunities.

Please take a moment to learn more about our conference by browsing our website or downloading our advance program.

To take full advantage of this outstanding event, register before September 18!

Special hotel rates are also available from the dedicated hotel registration page.

The committee and I look forward to seeing you in San Fransisco.

– Bruce Doris, S3S General Chair

 Photo Credit: Catherine Allibert

Photo Credit: Catherine Allibert

2014 IEEE S3S (SOI/3D/SubVt) – Oct. SF – top speakers lined up; paper submissions til 26 May

IEEE_EDS_header

IEEE International

SOI-3D-Subthreshold Microelectronics Technology Unified Conference

6-9 October 2014

Westin San Francisco Airport, Millbrae, CA

The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 26, 2014 (click here for submission guidelines).

 

IMG_1060_revu2

Photo Credit: Catherine Allibert

Last year, the first edition of the IEEE S3S conference, founded upon the co-location of the IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference was a great success with a 50% increase in attendance.

The conference will, this year again, hold two parallel sessions related to SOI and Subthreshold Microelectronics supplemented by a common session on 3D integration.

The 2014 edition of the conference already promises a rich content of high-level presentations.

 

 

Program

The plenary session will host Alice Wang (MediaTek), Bruno Terkaly (Microsoft) and Mark Edelstone (Morgan Stanley Investment Banking). They will give us a broad overview of the new markets and opportunities for the upcoming years.

Invited speakers from major industries (like GlobalFoundries, SEH, ST, IBM, Rambus) and from many prestigious academic institutions will share with us their views of the ongoing technical challenges related to SOI, Sub-VT and 3D integration. The complete list of invited speakers can be seen on the program outline page of the conference website.

On the same webpage, more information is given about the various dedicated sessions.

There will be two short courses again this year: One on Power Efficiency, and the other on Monolithic 3D. There will also be a class on RF-SOI Technology Fundamentals and Applications as well as a fundamentals class on Robust Subthreshold Ultra-low-voltage Design of Digital and Analog/RF Circuits.

The Hot Topics session will, this year, be about MEMS. During the Rump session we will debate about the Cost and Benefit of Scaling Beyond 14nm.

 

Scope of the conference

The Committee will review papers submitted by May 26 in the three following focus areas of the conference:

  • Silicon On Insulator (SOI): Ever increasing demand and advances in SOI and related technologies make it essential to meet and discuss new gains and accomplishments in the field. For over 35 years our conference has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-On-Insulator technology. Previously unpublished papers are solicited in all areas of SOI technology and related devices, circuits and applications.
  • Subthreshold Microelectronics: Ultra-low-power microelectronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. Ubiquitous sensor networks, RFID tags, implanted medical devices, portable biosensors, handheld devices, and space-based applications are among those that would benefit from extremely low power circuits. One of the most promising methods of achieving ultra-low-power microelectronics is to reduce the operating voltage to below the transistor threshold voltage, which can result in energy savings of more than 90% compared to conventional low-power microelectronics. Papers describing original research and concepts in any subject of ultra-low-power microelectronics will be considered.
  • 3D Integration, including monolithic 3D IC or sequential 3D IC, allows us to scale Integrated Circuits “orthogonally” in addition to classical 2D device and interconnect scaling. This session will address the unique features of such stacking with special emphasis on wafer level bonding as a reliable and cost effective method, similar to the creation of SOI wafers. We will cover fabrication techniques, bonding methods as well as design and test methodologies. Novel inter-strata interconnect schemes will also be discussed. Previously unpublished papers are solicited in all of the above areas related to 3D implementation.

Students are encouraged to submit papers and compete for the Best Student paper awards, sponsored by Qualcomm. Details on paper submission and awards are given on the call for paper webpage.

 

LocationIMG_0937-Revue

The 2014 edition of the conference will be very conveniently located in Millbrae, California, close to the San Francisco airport. The BART and Caltrain stations, within walking distance, give you access to San Francisco to the north and the Silicon Valley to the south. Conference attendants will be able to easily combine their trips with visiting colleagues in the Bay Area or touring the Golden City.

Important dates:

Paper submission deadline: 26 May 2014

Notification of acceptance: 23 June 2014

Short course date: 6 October 2014

Conference date: 6 – 9 October 2014

More details are available on the S3S website.

IMG_1037_revu2

Photo Credit: Catherine Allibert

 

GPU/CPU on SOI: the Xbox 360 did it first

Microsoft and IBM moved the CPU and the GPU of the best-selling game console in North America onto a single SoC – a year ahead of the pack.

There’s a lot of excitement about the “latest trend” of integrating both the computing chip – the CPU and the graphics chip – the GPU – into a single chip. But in fact, the first GPU/CPU system-on-chip (SoC) came out in June 2010. It’s on 45nm SOI, is produced by multiple foundries, and is at the heart of the hottest selling game console in North America: the Xbox 360.

 

Xbox 360 GPU/CPU SoC Chip Statistics:
• 372M transistors
• 45nm SOI, Ultra-low k dielectric
• 10 levels of metal
• 153 array types, ~1000 instances
• 1.8 million flip flops
• 6 PLLs
• 12 clock domains
• Compared to 2005 CPU GPU:
• >60% Power Reduction
• >50% Silicon Area Reduction
(Courtesy: IBM & Microsoft)

The technical community refers to it as the Xbox 360 S – “S” for “slim”, because the new chip enabled a host of slimming effects. The two most important were a slimmed-down power budget (43% less than the previous generation) and a serious reduction in the bill-of-materials (always good news for the bottom line).

Power down

You might think that the GPU/CPU combo also provided a major performance boost. But in fact, for game console lifetimes, one thing you can’t do is toy much with performance. Game developers count on having a stable platform – they need it to work just the way they first planned it for the entire console life cycle.

One of the advantages SOI gives to chip designers is that it’s a powerful “knob to turn” – they can ratchet up performance (and keep about the same some power budget), or drastically reduce power (in exchange for a less dramatic performance increase), or they can find a balance somewhere in between.

In the case of the Xbox 360 GPU/CPU, one can surmise that since they couldn’t boost performance too much, they had the luxury of turning the knob way down for power. And that translates into a whole lot of benefits.

But first let’s look at what they actually did.

2 for 1

The first Xbox 360 came out in 2005, with a CPU on 90nm SOI (see ASN #6) and a GPU on 90nm bulk. A few years later, the chips were migrated to 65nm. Then in 2010, the two were combined on a single chip using 45nm SOI.

For the IBM and Microsoft chip design team, the latest challenge involved both a port (the bulk GPU to SOI), a shrink (to 45nm) and a complete redesign of the GPU (which had originally been designed by ATI). However, from a graphics standpoint, the resulting chip had to remain functionally identical to the old GPU, to ensure the backward compatibility of the games.

It also involved removing the front-side bus (FSB), which handles functional intercommunication between the CPU and GPU blocks.

The Xbox 360 CPU and GPU process migration history. (Courtesy: IBM and Microsoft)

Compared to having two chips, putting the two units into one chip saved 60% in power and 50% in area compared to the 90nm versions.

Savings abound

In terms of silicon, the savings are obvious when you’re fabbing one chip instead of two. However, the ramifications for savings extend far beyond the silicon.

Consider thermal design, for example. Instead of cooling two chips, you just have one: so one heatsink; one fan. And with good thermal management, the fan speed is lower – so it’s significantly quieter and needs less power for the fan.

 

Left: The final 35mm x 35mm package includes the integrated GPU/CPU and an eDRAM. (Courtesy: IBM & Microsoft)
Right: The GPU/CPU SoC simplified the motherboard layout. (Courtesy: Microsoft & IBM)

This simplifies the motherboard layout and power delivery. And of course, between the lower power chip and the slower fan speeds, they could use a smaller power supply unit.

All these factors combined to enable a reduction in console size. However, the new chip is robust enough to also seamlessly handle the high-performance processing for Microsoft’s Kinect – the new motion sensor that replaces the controller.

 

The new Xbox 360 GPU/CPU also handles the processing for the Kinect motion sensor. (Courtesy: Microsoft)

In January 2011, Microsoft announced that the new Xbox 360 had just capped off six consecutive months as the best-selling console in North America. More than 50 million Xbox 360 consoles have been sold worldwide – double the amount of the previous generation Xbox.

Sales are up 27% year on year, and Microsoft has indicated that this console should keep going strong through 2015. Which shows that great things happen – and keep happening – on SOI.

A special thanks to Bob Drehmel of IBM for his technical guidance on this article.

The New Generation: It’s All On SOI

The PS3, Wii and Xbox 360 CPU design teams all chose SOI. Here’s why.

(Courtesy: Sony Computer Entertainment Europe)

PlayStation®3 “Cell” CPU. Jointly developed by IBM, Sony and Toshiba. Manufactured by IBM and Sony. (Courtesy: IBM)

Design challenges
(Read the Cell overview paper by Kahle et al on the IBM website)
Achieve 100 times the PlayStation®2 performance. Joint developers IBM, Sony Group and Toshiba needed to co-optimize the chip area, design frequency, and product operating voltage, creating a “supercomputer on a chip” that marries broadband interconnect, entertainment systems, and supercomputer structures. Beyond the PlayStation®3, the three companies would each promote Cell-based products ranging from digital televisions to home servers to supercomputers.

Solution
Multi-core SoC architecture featuring eight synergistic processors (PowerPC-base Core @3.2GHz, 8 x SPE @3.2GHz). 234 million transistors. 90nm SOI CMOS.

Result
SOI provides a significant power/performance advantage.

(Courtesy: Nintendo)

Wii™ CPU. Jointly developed by Nintendo and IBM. Manufactured by IBM. (Courtesy: IBM)

Design challenges
(Read the full interview with the lead chip designer on the Nintendo website)
Wii console to be no bigger than a stack of three DVD cases so it fits inconspicuously next to a TV and can be left on 24 hours a day. Need lower power consumption and higher performance in a smaller chip. Small case incurs severe heat restrictions.

Solution
Custom PowerPC (code-named “Broadway”) on 90nm SOI CMOS.

Result
SOI technology from IBM helps deliver to Nintendo a generous improvement in processing power while achieving a 20 percent reduction in energy consumption.

(Courtesy: Microsoft)

Xbox™360 CPU. Jointly developed by Microsoft and IBM. Manufactured by IBM and Chartered.(Courtesy: IBM DeveloperWorks)

Design challenges
Ground-up design specifically for high-definition gaming and entertainment. Chip design from concept to full execution in 24 months. Pack twice the power of the Xbox into a smaller form factor. Give game designers power where they need it.

Solution
A customized version of IBM’s 64-bit PowerPC core. The chip includes three of these cores, each with two simultaneous threads and clock speeds greater than 3.2 GHz. 165 million transistors. 90nm SOI CMOS, transitioning to 65nm SOI in Q107.

Result
SOI technology reduces heat and improves performance.

Chartered’s SOI Success Story

Chartered is the industry’s first pure-play foundry to expand into high-volume SOI production.

High-volume SOI at Chartered Semiconductor Manufacturing is a great success. January 2007 marks the three-year anniversary of the initial announcement that we would manufacture 90nm SOI products for IBM in volume-driven, high-performance solutions. Since we ramped production in mid-2005, we have shipped product on over 65K SOI wafers. Read More

Two important SOI-related announcements from Chartered

• Two important SOI-related announcements from Chartered. It is licensing IBM ’s 90 nm SOI technology, enabling it to expand the use of the technology to areas such as consumer, multi-media, communications, automotive and industrial applications for foundry customers. And, following the successful manufacturing of 90 nm SOI CPU products for the Xbox 360, Chartered has signed an agreement with Microsoft for manufacturing a 65 nm SOI version of the Xbox 360 CPU.

Nintendo has announced that the CPU of its new Wii® game console is based on a PowerPC

Nintendo has announced that the CPU of its new Wii® game console is based on a PowerPC (code-named “Broadway”) made with a 90 nm SOI CMOS process, jointly developed with and manufactured by IBM. The design was optimized with state-of-theart processing technologies that minimize power consumption and keep the console compact.

The confirmation of Nintendo Wii marks a IBM/SOI grand slam: all three of the leading new-generation game consoles (Sony PlayStation®3, Microsoft Xbox® 360 and Nintendo Wii®) are based on the company’s SOI CMOS processes.

EE Times Ace Awards Again Honor SOI Innovators

Freescale’s Leo Mathew was chosen for his novel transistor structure. IBM & Microsoft Design Teams win for Xbox 360™


Leo Mathew, a principal solid state engineer at Freescale Semiconductor, was named Innovator of the Year at the EE Times Annual Creativity in Electronics (ACE) awards ceremony, for his invention of a novel transistor structure. His inverted T-channel field-effect transistor (ITFET) combines vertical and horizontal structures into a single transistor. The device was fabricated using innovative 90nm SOI CMOS process techniques at Freescale’s Austin Technology & Manufacturing Center.

Freescale CEO Michel Mayer won the ACE Executive of the Year award, for leading the company to seven consecutive quarters of profitability, re-energizing the corporate culture and starting to build a global brand.

IBM and Microsoft received the ACE Design Team of the Year award for the SOI-based Xbox 360.

SOI By Design

The widening availability of tools and services is good news for designers in the fabless/foundry arena considering the move to SOI.

Leading foundries have made the investments in manufacturing on SOI. Those that have taken the final steps – finalizing electrical characterization, constructing SPICE models, integrating design tools and building libraries – are winning business.

Chartered, for example, is producing SOI-based chips for AMD, the Microsoft Xbox®360, Via, and others in partnership with IBM. TSMC, meanwhile has announced an SOI version of its Nexsys 65nm process technology for next year.

For the high-performance fabless community, IBM itself was the first to open SOI doors to its foundry customers. Ghavam Shahidi, Director of Silicon Technology, IBM Research Division, says they see the full range – from customers that do the whole thing themselves, just getting the IBM-specific SOI IP, to those who essentially hand off the whole project to the IBM services group. Asked how big a challenge the move to SOI is, he says, “It’s not a big deal – it seems scarier than it is.”

As far as those low-power customers worried about the added cost of SOI wafers, he suggests that if they were to consider the broader picture and include things like cooling, they might find it a more cost-effective solution.

In the Flow

Design flow involves a series of iterative steps subject to rules and constraints – many of which are different when devices are built in SOI. SOI-specific IP is needed at each step, especially:

• In support of the logic synthesis tools used to transform the high-level RTL design into a gate-level netlist (which is the collection of “standard cells” and their electrical interconnections specific to the foundry that will do the manufacturing).

• And in the placement and routing tools to layout the chip. Either the design team has to develop SOIspecific expertise (a substantial investment), or license intellectual property (IP) from a third party (the foundry or an IP vendor).

By licensing the requisite IP, designing-in SOI becomes a transparent process. As the designer generates netlists and optimizes placement and routing, the SOI IP is applied via standard EDA tools from companies like Cadence, Synopsys and Magna.

TCAD from Synopsys, for example, can model the SOI technology from the process and device simulation standpoint, so performance of SOI and bulk silicon can be compared before choosing the right technology for the design, says a company representative. Also, engineers can optimize the SOI technology by using TCAD simulation before running costly experimental wafers.

Says Francois Thomas, Europe ICD & DFM Field Marketing Director for Cadence Design Systems, “SOI uses nearly standard processes and design but with better performance. The real difference appears for cell creation, analog simulation and DRC and parasitic extraction.”

SOI IP Vendors

Recently three new SOI IP and design services suppliers have helped bring SOI design to a wider community.

Cell layout of SOISIC standard cells library for 90nm SOI process. (Courtesy of Soisic.)

Soisic. Working with companies that pioneered SOI, Soisic developed extensive design expertise and intellectual property (IP), which is now available to any ASIC designer. For a simple licensing fee, a design team can transparently integrate the SOI-specific design considerations into the design flow – without a special understanding of SOI (things like the history effect, for example) and the differences with bulk. No additional investment in time, training or libraries is needed

Innovative Silicon (ISi). ISi has harnessed the SOI “floating body effect” for memory cells that are twice as dense as existing DRAM and five times as dense as existing SRAM. This proprietary “Z-RAM™” (for Zero capacitor DRAM) technology uses standard SOI logic processes without new materials or extra process or masking steps. For most SoC and microprocessor ICs, this results in SOI being a lower-cost solution than bulk silicon. AMD is the first licensee.

CISSOID. As a fabless player, CISSOID designs custom analog, mixed and digital ASICs, with a specialty in SOI-based high temperature components for oil & gas, aeronautics, space and automotive applications. For low-power and RF applications, CISSOID offers design services, IP development and consulting for optimization of SOI analog and RF circuits.

Mixed Signal & RF Choices

For designers of mixed-signal, analog and RF devices, a growing number of major foundries have been actively promoting their SOI services.

For example, Honeywell offers RF SOI foundry services, supported by a comprehensive tool set and optional design services. The company points out that the SOI-enabled integration of mixed signal and high-voltage applications with complex control functions performed at low power on a single chip ultimately reduces cost.

Others like Atmel promote their SOIbased smart power foundry services for automotive, telecommunications and consumer electronics, noting that using SOI cuts the die-area in half compared to standard bulk technology. The X-Fab foundry service offers SOI-based analog/mixed-signal and MEMS.

All things considered, SOI is now well within the grasp of the greater chip design community.

Xbox® 360 Debuts New Gaming Generation

Microsoft’s custom PowerPC chip by IBM is based on SOI

 

Microsoft’s Xbox 360, which is expected to fly out of the stores this holiday season, has some very impressive figures to cite. The three-core PowerPC-based CPU, custom-made for Microsoft by IBM, boasts one teraflop of floating-point performance. Read More