The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco.
Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S conference was successful by any measurement. The first year of the new conference leading-edge experts from 3D Integration, Sub-threshold Microelectronics and SOI fields gathered and we established a world class international venue to present, learn and debate about these exciting topics. The overall participation at the first year of the new conference grew by over 50%, and the overall quality and quantity of the technical content grew even more.
This year we are looking forward to continuing to enhance the content of the 2014 S3S Conference.
Short courses: Monolithic 3D & Power-Efficient Chip Tech
On Monday, Oct. 6 we will feature two Short Courses that will run in parallel. Short courses are an educational venue where newcomers can gain overview and generalists can learn more details about new and timely topics.
The short course on Monolithic 3D will be a full day deep dive into the topic of three-dimensional integration wherein the vertical connectivity is compatible with the horizontal connectivity (10,000x better than TSV). Already there are extremely successful examples of monolithic 3D Flash Memory. Looking beyond this initial application, we will explore the application of monolithic 3D to alternate memories like RRAM, CMOS systems with silicon and other channel materials like III V. In addition, a significant portion of the short course will be dedicated to the exciting opportunity of Monolithic 3D in the context of CMOS Logic.
The other short course we will offer this year is entitled Power Efficient Chip Technology. This short course will address several key aspects of power-efficiency including low power transistors and circuits. The course will also review in detail the impact of design and architecture on the energy-efficiency of systems. The short course chairs as well as the instructors are world class leading experts from the most prestigious industry and academic institutions.
The regular conference sessions will start on Tuesday Oct. 7 with the plenary session, which will feature presentations from Wall Street (Morgan Stanley Investment Banking), Microsoft and MediaTek. After the plenary session we will hear invited talks and this year’s selection of outstanding papers from international researchers from top companies and universities. The most up to date results will be shared. Audience questions and one on one interaction with presenters is encouraged.
Back by popular demand we will have 2 Hot Topics Sessions this year. The first Hot Topic Session is scheduled for Tuesday Oct. 7th and will feature exciting 3DI topics. The other Hot Topics session is scheduled for Thursday Oct 9 and will showcase new and exciting work in the area of MEMS.
Our unique poster session and reception format will have a short presentation by the authors followed by one on one interaction to review details of the poster with the audience, in a friendly atmosphere, around a drink. Last year we had regular posters as well as several invited posters with very high quality content and we anticipate this year’s poster session to be even better than last years.
We are offering a choice of two different fundamentals classes on Wednesday afternoon. One of the Fundamentals classes will focus on Robust Design of Subthreshold Digital and Mixed Circuits, with tutorials by the worlds leading experts in this field. The SOI fundamentals course is focused on RF SOI Technology Fundamentals and Applications.
Our technical content is detailed on our program webpage.
Panel discussions, cookout & more
Keeping in line with tradition, on Wednesday night we will have a hearty cook out with delicious food and drink followed by the Panel Session entitled Cost and Benefit of Scaling Beyond 14nm. Panel speakers from financial, semiconductor equipment, technology, and academic research institutions will gather along with the audience to debate this timely topic. Although Thursday is the last day of the conference we will have stimulating presentations on novel devices, energy harvesting, radiation effects along with the MEMS Hot Topic Session and Late News Session. As always we will finish the conference with the award ceremony for the best papers.
Our conference has a long tradition of attracting presenters and audience members from the most prestigious research, technology and academic institutions from around the world. There are many social events at the S3S Conference as well as quiet time where ideas are discussed and challenged off line and people from various fields can learn more about other fields of interest from leading experts.
The conference also offers many opportunities for networking with people inside and also outside ones area. The venue this year is San Francisco. We chose this location to attract the regions leading experts from Academia and Industry. If you have free time we encourage you to explore San Francisco which is famous for a multitude of cultural and culinary opportunities.
To take full advantage of this outstanding event, register before September 18!
Special hotel rates are also available from the dedicated hotel registration page.
The committee and I look forward to seeing you in San Fransisco.
– Bruce Doris, S3S General Chair
SOI-3D-Subthreshold Microelectronics Technology Unified Conference
6-9 October 2014
Westin San Francisco Airport, Millbrae, CA
Last year, the first edition of the IEEE S3S conference, founded upon the co-location of the IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference was a great success with a 50% increase in attendance.
The conference will, this year again, hold two parallel sessions related to SOI and Subthreshold Microelectronics supplemented by a common session on 3D integration.
The 2014 edition of the conference already promises a rich content of high-level presentations.
The plenary session will host Alice Wang (MediaTek), Bruno Terkaly (Microsoft) and Mark Edelstone (Morgan Stanley Investment Banking). They will give us a broad overview of the new markets and opportunities for the upcoming years.
Invited speakers from major industries (like GlobalFoundries, SEH, ST, IBM, Rambus) and from many prestigious academic institutions will share with us their views of the ongoing technical challenges related to SOI, Sub-VT and 3D integration. The complete list of invited speakers can be seen on the program outline page of the conference website.
On the same webpage, more information is given about the various dedicated sessions.
There will be two short courses again this year: One on Power Efficiency, and the other on Monolithic 3D. There will also be a class on RF-SOI Technology Fundamentals and Applications as well as a fundamentals class on Robust Subthreshold Ultra-low-voltage Design of Digital and Analog/RF Circuits.
The Hot Topics session will, this year, be about MEMS. During the Rump session we will debate about the Cost and Benefit of Scaling Beyond 14nm.
The Committee will review papers submitted by May 26 in the three following focus areas of the conference:
Students are encouraged to submit papers and compete for the Best Student paper awards, sponsored by Qualcomm. Details on paper submission and awards are given on the call for paper webpage.
The 2014 edition of the conference will be very conveniently located in Millbrae, California, close to the San Francisco airport. The BART and Caltrain stations, within walking distance, give you access to San Francisco to the north and the Silicon Valley to the south. Conference attendants will be able to easily combine their trips with visiting colleagues in the Bay Area or touring the Golden City.
Paper submission deadline: 26 May 2014
Notification of acceptance: 23 June 2014
Short course date: 6 October 2014
Conference date: 6 – 9 October 2014
More details are available on the S3S website.