This is part 2 (of 2) of ASN’s coverage of the epic FD-SOI Symposium in San Jose. In part 1 we looked at the exciting developments happening at 28nm (if you missed it, click here to read it now). Here in part 2, we’ll look at 22nm, covering the presentations by GlobalFoundries, ARM, VLSI Research and Sigma Designs. Again, the presentations are now starting to be available on the SOI Consortium website – click here to see them (they’re not all there as of today, though, so keep checking back).
Dan Hutcheson, CEO of VLSI Research, has come around to FD-SOI. His excellent talk, “FD-SOI: Disruptive or Just Another Process” (click here to download it), concluded that FD-SOI is not disruptive – but it’s an enabler of disruption. The disruption is IoT, and it’s going to be a big one. To prepare for his talk, he did an informal survey of designers at a dozen top companies. Here are some of the things he heard:
Some companies are using FinFET for some chips and FD-SOI for others, depending on the market they’re targeting – either way, the technologies will co-exist. FinFETs were generally chosen for high-density chips from large companies with lots of money; FD-SOI by those who have time-to-market constraints, are looking to differentiate their products, appreciate the much lower NRE* costs, and that are going for power, reliability and analog advantages.
People see a future with FD-SOI – it’s not a one-trick process.
The design community is happy to be able to re-use many of their favorite techniques that were lost after the 130nm node.
Top target markets for FD-SOI are (by far) IoT, automotive and low-power, followed by analog/mixed-signal, networks, RF, low-end products, mobile, peripherals, MPU/GPU, image sensors and rad-hard.
Here are a couple of his slides that sum up the technical and business reasons people cited as reasons for going to FD-SOI:
Dan then made a video recapping his San Jose presentation – it’s awesome – click here to see it.
The ballroom packed right out when GloFo VP Subramani Kengeri took the stage to present, “Enabling Next Generation Semiconductor Product Innovations with 22FDXTM.
In terms of energy efficiency, he explained, 0.4V is the minimum energy point for almost any technology – and FD-SOI gets you 0.4V. He then went on to reiterate the features of GloFo’s 22FDXTM Platform, the industry’s first 22nm FD-SOI:
Ultra-lower power with 0.4 volt operation
Software-controlled transistor body-biasing for innovative performance and power optimization
Delivers FinFET-like performance and better energy-efficiency at 28nm-like cost
Integrated RF: reduced system cost, and back-gate feature to reduce RF power up to ~50%
Integrated eNVM and RF enables lowest cost and smallest form-factor
Post-Silicon Tuning/Trimming for Analog/RF, SRAM and Power/Performance optimization
Enables innovative applications across mobile, IoT and RF markets
70% lower power than 28HKMG, 20% smaller die than 28nm bulk planar
Lower die cost than FinFETs
He then gave lots of technical details (the whole presentation is now available for download from the SOI Consortium website – click here to get it). A key point is that FD-SOI will scale to 7nm. Here’s the slide that says it all:
Also, be sure to check out the Cadence presentation when it’s posted – it looks at the solid design methodology now in place.
Following a brief mea culpa acknowledging that ARM had been missing too long from the FD-SOI table, GM of the Physical Design group Will Abbey made it clear that they are now fully onboard. In his talk, “Realize the Potential of FD-SOI”, he said in comparisons between 22nm FD-SOI and 14nm FinFET, they see a lot of space for FD-SOI. Here’s his summary slide:
They are now looking at ways to further optimize back-biasing to decrease total power in block-level implementations. And yes, he said, you’ll get performance that’s close to FinFET.
Fabless innovator Sigma Designs is focused on the connected home (especially smart TV and media connectivity) and IoT. CEO Thinh Tran presented, “Enabling the Digital Connected World with FDSOI” – you can download it here.
If you really want to optimize for power efficiency, use FD-SOI and run at 0.4V, he advised. “I’m very excited about this,” he told the San Jose audience, adding that, “It’s especially good for RF.” Here’s his slide that explains why:
So, it was a great day in San Jose for 22nm and 28nm FD-SOI. Be sure to keep checking back at the SOI Consortium website, as more presentations will become available in the days to come.
~ ~ ~
*NRE = non-recurring engineering. In a fabless scenario, there are NRE for IP and design (engineering costs, up-front and royalty-based IP costs), NRE for masks and fabrication (mask costs, wafer prototype lots, tools costs, probe cards, load-boards and other one-time capital expenditures), and NRE for qualifications (ESD, latch-up and other industry-specific qualifications, as in automotives).
The #1 take-away message from the recent FD-SOI Symposium in San Jose is that “FD-SOI is the smart path to success”. With presentations echoing that theme by virtually all the major players – including (finally!) ARM – to a packed house, it really was an epic day for the FD-SOI ecosystem. The presentations are now starting to be available on the SOI Consortium website – click here to see them (they’re not all there as of today, though, so keep checking back).
Since there’s so much to cover, we’ll break this into two parts. This is Part 1, focusing on presentations related to some of the exciting products that are hitting the market using 28nm FD-SOI. Part 2 will focus on the terrific presentations related to 22nm FD-SOI. In future posts we’ll get into the details of many of the presentations. But for now, we’ll just hit the highlights.
So back briefly to FD-SOI being smart. (A nice echo to the Soitec FD-SOI wafer manufacturing technology – SmartCutTM – that make it all possible right?) It started with the CEO of Sigma Designs (watch for their first IoT products on FD-SOI coming out soon) quipping, “FD-SOI is the poor man’s FinFET.” To which GlobalFoundries’ VP Kengeri riffed that really, “FD-SOI is the smart man’s FinFET”. And NXP VP Ron Martino, summed it up saying, “FD-SOI is the smart man’s path to success”. Yes!
Samsung now has a strong 28nm FD-SOI tape-out pipeline for 2016, and interest is rising fast, said Kelvin Low, the company’s Sr. Director of Foundry Marketing. His presentation title said it all: “28FDS – Industry’s First Mass-Produced FDSOI Technology for IoT Era, with Single Platform Benefits.” They’ve already done 12 tape-outs, are working on 10 more now for various applications: application processor, networking, STB, game, connectivity,…., and see more coming up fast and for more applications such as MCU, programmable logic, IoT and broader automotive. It is a mature technology, he emphasized, and not a niche technology. The ecosystem is growing, and there’s lots more IP ready. 28nm will be a long-lived node. Here’s the slide that summed up the current production status:
As you see, the production PDK with the RF add-on will be available this summer. Also, don’t miss the presentations by Synopsys (get it here), which has repackaged the key IP from ST for Samsung customers, Leti on back-bias (get it here), Ciena (they were the Nortel’s optical networking group) and ST (it’s chalk-full of great data on FD-SOI for RF and analog).
If you read Ṙon’s terrific posts here on ASN recently, you already know a lot about where he’s coming from. If you missed them, they are absolute must-reads: here’s Part 1 and here’s Part 2. Really – read them as soon as you’re done reading this.
As he noted in his ASN pieces, NXP’s got two important new applications processor lines coming out on 28nm FD-SOI. The latest i.MX 7 series combines ultra-low power (where they’re dynamically leveraging the full range of reverse back biasing – something you can do only with FD-SOI on thin BOX) and performance-on-demand architecture (boosted when and where it’s needed with forward back-biasing). It’s the first general purpose microprocessor family in the industry’s to incorporate both the ARM® Cortex®-A7 and the ARM Cortex-M4 cores (the series includes single and dual A7 core options). The i.MX 8 series targets highly-advanced driver information systems and other multimedia intensive embedded applications. It leverages ARM’s V8-A 64-bit architecture in a 10+ core complex that includes blocks of Cortex-A72s and Cortex-A53s.
In his San Jose presentation, Ron said that FD-SOI is all about smart architecture, integration and differentiating techniques for power efficiency and performance. And the markets for NXP’s i.MX applications processors are all about diversification, in which a significant set of building blocks will be on-chip. The IoT concept requires integration of diverse components, he said, meaning that a different set of attributes will now be leading to success. “28nm FD-SOI offers advantages that allows scaling from small power efficient processors to high performance safety critical processor,” he noted – a key part of the NXP strategy. Why not FinFET? Among other things, it would bump up the cost by 50%. Here are other parts of the comparison he showed:
For NXP, FD-SOI provides the ideal path, leading to extensions of microcontrollers with advanced memory. FD-SOI improves SER* by up to 100x, so it’s an especially good choice when it comes to automotive security. Back-biasing – another big plus – he calls it “critical and compelling”. The icing on the cake? “There’s so much we can do with analog and memory,” he said. “Our engineers are so excited!”
You know how using mapping apps on your smartphone kills your battery? Well now there’s hope. Sony’s getting some super impressive results with their new GPS using 28nm FD-SOI technology. These GPS are operated at 0.6V, and cut power to 10x (!) less than what it was in the previous generation (which was already boasting the industry’s lowest power consumption when it was announced back in 2013).
In San Jose, Sony Senior Manager Kenichi Nakano presented, “Low Power GPS design with RF circuit by the FDSOI 28nm”, proclaiming with a smile, “I love FD-SOI, too!” All the tests are good and the chip is production ready, he said. In fact, they’ve been shipping samples since March.
As of this writing, his presentation is not yet posted. But til it is, if you’re interested in the background of this chip, you can check out the presentation he gave in Tokyo in 2015 here.
SERDES (Serializer/Deserializer) IP is central to many modern SOC designs, providing a high-speed interface for a broad range of applications from storage to display. It’s also used in high-speed data communications, where it’s had a bad rep for pulling a huge amount of power in data centers. But Analog Bits has been revolutionizing SERDES IP by drastically cutting the power. Now, with a port to 28nm FD-SOI, they’re claiming the industry’s lowest power.
In his presentation, “A Case Study of Half Power SERDES in FDSOI”, EVP Mahesh Tirupattur described FD-SOI as a new canvas for chip design engineers. The company designs parts for multiple markets and multiple protocols. When they got a request to port from bulk to 28nm FD-SOI, they did it in record time of just a few months, getting power down to 1/3 with no extra mask steps. Plus, they found designing in FD-SOI to be cheaper and easier than FinFET, which of course implies a faster time to market. “The fabs were very helpful,” he said. “I’m pleased and honored to be part of this ecosystem.”
Listening to a presentation by Stanford professor Boris Murmann gets you a stunning 30,000 foot view of the industry through an amazing analog lens. He’s lead numerous explorations into the far reaches of analog and RF in FD-SOI, and concludes that the technology offers significant benefits toward addressing the needs of: ultra low-power “fog” computing for IoT (it’s the next big thing – see a good Forbes article on it here); densely integrated, low-power analog interfaces; universal radios; and ultra high-speed ADC. Get his symposium presentation, “Mixed-Signal Design Innovations in FD-SOI Technology” here.
So, it was a great day in San Jose for 28nm FD-SOI. Next in part 2, we’ll look at why it was also an epic day for 22nm FD-SOI. Be sure to keep checking back at the SOI Consortium website, as more presentations will become available in the days to come.
~ ~ ~
*SER = Soft Error Rates – soft errors occur when alpha or neutron particles hit memory cells and change their state, giving an incorrect read. These particles can either come from cosmic rays, or when radioactive atoms are released into the chips as materials decay.
The SOI Consortium has lined up an excellent, comprehensive FD-SOI Symposium on April 13th in San Jose. They’ll be highlighting the tremendous progress of the FD-SOI ecosystem. Headliners include Cisco, Sony, NXP, SigmaDesigns, ARM, Ciena plus the big FD-SOI foundries, EDA companies, design partners, chipmakers and analysts. There is a special session dedicated to RF and analog design innovation on FD-SOI with STMicroelectronics, Stanford and others. In short, we’re going to get a chance to see the FD-SOI ecosystem in action.
To attend, all you have to do is register in advance – click here to go to the registration page. It’s free and open to everyone who registers.
08:00AM – 09:00AM – Registration
08:55AM – 09:00AM – Welcome by Carlos Mazure, SOI Consortium
09:00AM – 09:30AM – Aglaia Kong, Cisco Systems, CTO for Internet of Everything
09:30AM – 10:00AM – Thinh Tran, Sigma Designs, CEO
10:00AM – 10:30AM – Ron Martino, NXP, VP, Application Processors & Advanced Technology Adoption
10:30AM – 10:50AM – Coffee Break
10:50AM – 11:20AM – Subramani Kengeri, GLOBALFOUNDRIES, VP CMOS Business Unit
11:20AM – 11:50AM – Will Abbey, ARM, GM Physical IP
11:50AM – 12:20PM – Kelvin Low, Samsung Semiconductor, Senior Director, Foundry Marketing
12:20PM – 1:40PM Lunch
1:40PM – 2:10PM – Kenichi Nakano, SONY, Sr. Manager, Analog LSI Business Division
2:10PM – 2:40PM – Dan Hutcheson, VLSI Research, CEO
2:40PM – 3:05PM – Mahesh Tirupattur, Analog Bits, EVP
3:05PM – 3:30PM – Mike McAweeney, Synopsys, Sr. Director, IP Division
3:30PM – 4:00PM – Coffee Break
4:00PM – 4:30PM – Naim Ben-Hamida, Ciena, Senior Manager
4:30PM – 4:55PM – Rod Metcalfe, Cadence, Group Director, Product Engineering
4:55PM – 5:20PM – Prof. Boris Murmann, Stanford, on “Mixed-Signal Design Innovations in FD-SOI Technology”
5:20PM – 5:45PM – Frederic Paillardet, STMicroelectronics, Sr. Director, RF R&D
5:45PM – 6:00PM – Ali Erdengiz, CEA-LETI, Silicon Impulse
6:00PM – 6:05PM – Closing remarks by Giorgio Cesana, SOI Consortium
Please note that if you’ve already registered last month when the first announcement went out, the location has changed. The SOI Consortium FD-SOI Symposium will be held on Wednesday, 13 April 2016, from 8am to 6:30pm at the:
Doubletree Hotel San Jose
2050 Gateway Place
San Jose, California 95110, USA
If you can’t make it, not to worry – ASN will be there taking notes for a round-up and follow-up articles. Plus we’ll be tweeting and retweeting (follow us on Twitter at @FollowASN and @AdeleHars – look for the hashtag #FDSOI). And of course you’ll want to follow the Twitter feeds of participating companies, and of the SOI Consortium @SOIConsortium.org.
By: Tamer Ragheb, Digital Design Methodology Technical Manager at GlobalFoundries and Josefina Hobbs, Senior Manager of Strategic Alliances, Synopsys
It’s clear that getting an optimal balance of power and performance at the right cost is foremost in the minds of designers today. Designers who want either high performance or ultra low-power, or ideally both, have a choice to make when it comes to migrating to next generation nodes. For applications that push the envelope in performance, FinFET would be the optimal solution. For applications that require ultra low-power and more RF integration, FD-SOI is the right solution. The two technologies have different value propositions that need to be considered while designing for applications ranging from high-performance computing and server to high-end mobile and Internet of Things (IoT).
GlobalFoundries 22FDX is the industry’s very first 22nm FD-SOI platform. The 22FDX technology is specifically designed to meet the ultra low-power requirements of the next generation of connected devices. The big advantage of this platform is its ability to provide software control at the transistor level through flexible body-biasing (Fig. 1). The ability to provide real-time trade-offs between power and performance via software-controlled body-biasing of the transistor creates new options for the designer. For example, imagine designing a processor for a Smartwatch that could match its power-performance tradeoff to your typical use and modify its performance based on how you’re using it that day.
The full impact of the body bias capability of 22FDX becomes clear when compared to incumbent high-performance process technologies (Fig. 2). 22FDX compared to a 28nm high K metal gate (HKMG) technology can provide up to 50% less power at the same frequency, or 40% faster performance at the same total power than 28HKMG. In addition, 22FDX can be further optimized with forward body bias, shown on the blue curve, to further reduce the power or to further boost the speed in a turbo operation mode.
In addition to the body bias, 22FDX offers capabilities for design flexibility and intelligent control that are not available in other technologies. These include:
Manufacturing success is highly sensitive to specific physical design features, with advanced nodes requiring more complex design rules and more attention to manufacturability issues on the part of designers. However, there are essentially no additional manufacturing requirements to design in 22FDX beyond what is required for 28nm designs.
There are four application optimized extensions available with 22FDX (Fig. 3). These are:
GlobalFoundries reference flow for 22FDX has been optimized to support forward and reverse body bias (FBB/RBB), which provides the design flexibility to optimize the performance/power trade-offs. The reference flow supports implant-aware and continuous diffusion-aware placement, tap insertion and body bias network connectivity according to high voltage rules, double-patterning aware parasitic extraction (PEX), and design for manufacturing (DFM). This provides designers with the flexibility to manage power, performance and leakage targets for the next-generation chips used in mainstream mobile, IoT and networking applications.
GlobalFoundries has been collaborating with Synopsys to enable and qualify their tools for the 22FDX Reference Flow. The recent qualification of Synopsys’ Galaxy™ Design Platform for the current version ofGlobalFoundries’ 22FDX technology allows the designer to manage power, performance and leakage and achieve optimal energy efficiency and cost effectiveness. Synopsys’ Galaxy Design Platform supports body biasing techniques throughout the design flow, including both forward and reverse body bias, enabling power/performance trade-offs to be made dynamically and delivering up to 50% power reduction.
Key tools and features of the Galaxy Design Platform in the 22FDX reference flow include:
The 22FDX technology leverages existing design tools such as the Galaxy Design Platform, manufacturing infrastructure and the broader design ecosystem. This speeds time to market and enables the creation of differentiated products.
For this 3-part series, ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 3, we’ll talk about the ecosystem. (In part 1 we talked about technology readiness, and in part 2, we talked about design.)
~ ~ ~
ASN: Let’s talk a little more about IP availability.
Axel Fischer: The availability of IP is key for engaging these market segments. The technology itself is ready. The gating item often is the IP element.
Kelvin Low: The IP element is broadly ready. But we’re not stopping there. We’re enhancing the IP and adding on new suppliers. Most of them we can’t name yet just because of timing. But we can confidently say that multiple new IP suppliers are coming online, and many more have started to inquire about how they can get onboard.
ASN: In terms of the ecosystem, what remains to be done?
KL: The ecosystem can never end. Enhancements will always be welcome. More support – there are so many other EDA software companies out there available. We will enable them if there is a customer behind them. IP are dictated by the standards. As long as the product requires that, we’ll continue to look for partners to develop the IP.
KL: Back to one of the strategic decisions we made. We have immediately made available what ST Micro has in terms of IP portfolio to our customers. Then continuously build this ecosystem according to the new customers that we’re acquiring. ST Micro has developed these IPs for their own internal products, and they were gracious enough to allow these IPs to be opened up to be used by all customers without restriction.
As a group, as an ecosystem, we have to be more proactive in educating the market. What we’ve seen so far, whether it’s an initiative by Leti or an initiative by the SOI Consortium, these are very helpful. Now you have so many more knobs that you can play with, for designers we have to prepare all these PVT – which is process, voltage, temperature, and timing points so they can actually use it. It’s just a matter of preparation needed from our end, working with the ecosystem. The EDA tools must be optimized to make it as seamless, as transparent as possible.
ASN: Any closing thoughts?
KL: 28FDSOI is real. Samsung is committed. The technology is qualified already. The ecosystem is ready and expanding. This is working stuff. It’s not a powerpoint technology.
This is the last installment in ASN’s 3-part interview with Samsung on their 28nm FD-SOI foundry offering. If you missed the other parts, you can still read part 1 about technology readiness (click here), and part 2 on design considerations (click here).
For this 3-part series, ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 2, we’ll talk about design. (In part 1, we talked about Samsung’s technology readiness. In part 3, we’ll talk about the ecosystem.)
~ ~ ~
ASN: Let’s start by talking about value. What do you see as the key advantages of 28nm FD-SOI?
Kelvin Low: FD-SOI is wide-ranging. What I mean by this is for the designers, there are many design knobs available that you can use to achieve either high performance or ultra low power. That’s a an extremely valuable and important proposition. The wide dynamic performance-power range is achieved with FD-SOI’s body biasing ability. Though bulk technologies allow body biasing, it has a comparatively much narrower range.
Another key benefit is the super analog gain and properties of FD-SOI. I think moving forward, we’ll probably start to see more customers that are analog-centric. Later on, we’ll see this as one of the key value propositions of FD-SOI. Today, there’s still a lot of digital customers that we’re engaged with right now. The analog customers are still not yet aggressively migrating to [[more advanced]] technology nodes, but when they come, this will be an important distinction in FD-SOI vs. bulk.
Another important distinction not related to power-performance-area is the robustness of the reliability. This is a well-proven fact that FD-SOI is much more robust for soft-error immunity as compare to bulk. So anything that needs radiation protection (for example, military, aerospace – but those are not really the high-volumes), as well as automotive products, you’ll see value of better SER immunity as compared to bulk. Not just memory SER but logic SER. There are available design techniques to overcome / account for that. For example, if you design to overcome SER, you incur overhead in area for example. With FD-SOI, this is intrinsic, so you don’t need design tricks to suppress it.
ASN: When should designers consider using 28nm FD-SOI as opposed moving to 14nm FinFET or choosing another 28nm technology?
KL: By virtue of one being 28 and the other being 14, if you do need a lot of logic feature integration, or die-size reduction, 14nm will obviously become more necessary. If you just are looking for power savings, both 14nm FinFET and 28nm FD-SOI are fully depleted in nature, so both are able to operate with a lower power supply. So those are similarities. 14nm FinFET does provide higher performance compared to 28nm by virtue of how the process is constructed. Lastly, cost, which is related to the number of double-patterning layers – at 28nm, avoiding all the expensive double-patterning layers and 14nm having double-patterning being necessary for all the area scaling – that presents itself as a real difference. The end-product cost can also determine the choice of the technology selection.
Axel Fischer: The end-product cost, plus as well the investments from the customer side: the customer has to make a certain investment to develop the chip in terms of overall cost. If you look at photomask payment, NRE* and so on – this is weighting strongly, more and more as you go forward with advanced node technologies. There’s a set of customers that are feeling very comfortable to stay on the 28nm node.
KL: There are several 28nm flavors. There’s Poly-SiON, there’s HKMG, and there’s HKMG-FD-SOI. In terms of performance, there’s really a very clear distinction. In terms of power, you see a more radical power reduction with FD-SOI. In chip area scaling, I’d say roughly the same between HKMG and FD-SOI. This is dictated not so much by the transistor but by the overall design rules of the technology. So, 14nm is the higher cost point. 28nm is a much lower cost point, so overall a given budget that a customer has can determine whether 14nm is usable or otherwise. We have to sit down with the customer and really understand their needs. It’s not just trying to push one over the other solution. Based on their needs, we’ll make the proper recommendations.
ASN: Can designers get started today?
KL: We are moving FD-SOI discussions with customers to the next phase, which is to emphasize the design ecosystem readiness. So what we’ve been working on, and we really appreciate ST Micro’s support here, is to kick-start market adoption. We have access to ST Micro’s foundation library, and some of their foundation and basic IPs. Here, Samsung is distributing and supporting customers directly. They need to only work with us, and not with ST Micro. So they have access to the IP through us. We also provide design support, and we have additional IPs coming in to serve the customers from the traditional IP providers.
Many designers are new to body biasing. Fortunately, there are a couple of design partners that can help in this area. Synapse being one of them; Verisilicon another. Already, they have put in resources and plans and additional solutions to catalyze this market. In short, the PDK is available today, and the PDK supporting multi tools – Synopsys, Cadence and Mentor – are all available for download today. Libraries are also all available for download.
There’s nothing impeding designers from starting projects now. This is why we believe that 28FDSOI is the right node, because we are enabling the market to start projects today. If we start something else down the road, like a 14nm FD-SOI, for example, or something in between, the market will just say, hey, we like your transistor, we like your slides, but I have nothing to start my project on. So that is bad, because then it becomes a vicious cycle. We believe we have to enable 28nm designs now. Enable customers to bring actual products to the market. Eventually from there you can evolve 28 to something else.
ASN: Let’s talk some more about design considerations and body biasing, how it’s used and when.
KL: Both 14nm FinFET and 28nm FD-SOI are fully depleted. One unique technology value of fully-depleted architecture is the ability to operate the device at lower power supply. So power is the product of CV²/frequency. If you can operate this chip at lower power supply, you get significant dynamic power savings. FinFET does not have a body effect, so you cannot implement body biasing – it’s just not possible.
FD-SOI, on the other hand, has this extra knob – body biasing – that you can use. With reverse body bias (RBB), you can get much lower leakage power. If you want more performance, you can activate the FBB to get the necessary speed. Again, this is not possible with FinFET. So that will be one distinction. It depends on how you’re using your chip. It all depends on the system side, or even at the architecture side, how is it being considered already. If you’re already very comfortable using body biasing, then going to FinFET is a problem, because you’ve lost a knob. Some would rather not lose this knob because they see it as a huge advantage. That doesn’t mean you can’t design around it, it’s just different.
There are already users of body biasing for bulk. For customers that already use body biasing, this is nothing new. They’re pleased to now have the wider range, as opposed to the more narrow range for bulk.
AF: And probably going to FinFET is more disruptive for them. With FinFET, you have double-patterning considerations, etc. More capacitance to deal with.
ASN: Porting – does FD-SOI change the amount of time you have to budget for your port?
KL: If a customer already has products at 28nm, and they’re now planning the next product that has higher speed or better power consumption – they’re considering FinFET as one option, and now maybe the other option available is 28nm FD-SOI. The design learnings of going to FinFET are much more. So the port time will be longer than going to 28nm FD-SOI. We see customers hugely attracted because of this fact. Now they’re trying to make a choice. If it’s just a time-to-market constraint, sometimes FinFET doesn’t allow you to achieve that. If you have to tape out production in six months, you may have to use FD-SOI.
AF: Another key point for customers deciding to work with 28FDSOI is the fact that Samsung Foundry has joined the club. A few customers really hesitated on making the move to 28nm FD-SOI ST Micro is a very really advanced company, doing its own research and development, but the fact that the production capability was very limited has people shying away. Besides the technology, the presence and the engagement of Samsung is giving another boost to the acceptance.
KL: Yes, we’re recognized as a credible, high-volume manufacturing partner. That helps a lot.
~ ~ ~
*NRE = non-recurring engineering. In a fabless scenario, there are NRE for IP and design (engineering costs, up-front and royalty-based IP costs), NRE for masks and fabrication (mask costs, wafer prototype lots, tools costs, probe cards, loadboards and other one-time capital expenditures), and NRE for qualifications (ESD, latch-up and other industry-specific qualifications, as in automotives).
~ ~ ~
This is the second installment in ASN’s 3-part interview with Samsung on their 28nm FD-SOI foundry offering. If you missed the other parts, you can still read part 1 about technology readiness (click here), and part 3 on the ecosystem (click here).
ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 1, we’ll talk about technology readiness. In parts 2 and 3, we’ll talk about design and the ecosystem.
~ ~ ~
ASN: Where does Samsung stand in terms of rolling out your 28nm FD-SOI offer?
Kelvin Low: We have completed key milestones. Wafer level qualification was completed in September 2014, and then product level qualification in March 2015. So, the good news is the technology is fully qualified now.
What we have additionally in terms of overall technology readiness is production PDKs available right now. We have run a couple of MPWs already, and we’re scheduling more for next year. Silicon is really running in our fab. I think many may not have grasped that fact. Silicon is running, and we are running production for ST as one of our lead customers.
Axel Fischer: We already have a long relationship with ST – since 32 and 28nm HKMG bulk. We had a press release where we stated that more than a dozen projects had been taped out. EETimes published an article at the time. Adding 28 FD-SOI was a natural extension of an existing relationship
KL: That’s right –This is not a new customer scenario – it’s an existing customer, but an expansion of technology. And, in this case, it’s also a collaboration technology and IP solutions.
We are ST Micro’s primary manufacturing partner; this is one reason that it’s mutually beneficial for both of us. Crolles is not aiming for high volume. They prototype well. They do MPW and IP well, but they are not a high-volume fab. So, we complete the production rollout at Samsung Foundry.
ASN: Do you have other customers lined up?
KL: The short answer is yes. Beyond ST, Freescale can we talk about, since they have openly stated that they are using FD-SOI with us. Other customers, unfortunately, we just can’t say.But, they are in all the market segments (especially IoT) where the cost and ultra-low power combination is a very powerful one.
ASN: What about technology readiness and maturity?
KL: We have a couple of different 28 variants: the LPP, the LPH with more than a million wafers shipped. And because of that, our D0 – defect density – is at a very mature level. 28FD-SOI, sharing almost 75% of the process modules of 28 bulk, allows us to go to a very steep D0 reduction curve. We are essentially leveraging what we already know from the 28 bulk production experience. Defect density is essentially the inverse of yield. So, the lower the D0, the higher the yield.
This slide [[see above]] show the similarities between our FD-SOI and our 28 HKMG bulk. You can see how more than 75% of bulk modules are reused. The BEOL is identical, so its 100% reused. On the FEOL, some areas require some minor tuning and some minor modification, but anything that is specific to FD-SOI is less than 5% that we have to update from the fab perspective. All the equipment can be reused in the fab. There may be a couple of pieces related to the FD-SOI process that need to be introduced.Other than that, the equipment is being reused and can depreciated,.which is essential for any business. We leverage another lifetime for the tools.
ASN: When will we see the first high-volume FD-SOI chips? Next year?
KL: It depends on what market segment. Consumer, yes, I fully agree, they can ramp very fast. But other segments like infrastructure, networking or automotive, they’ll take a longer time to just qualify products.
AF: It’s not just us. If our customer needs to prove that the product is compliant with certain standards, you have to go through test labs and so on, this can be a very lengthy process. Product can actually be ready, and we’re all waiting to produce, but they’re still waiting for reports and the software that’s goes on top – this can be a very long cycle.
KL: We’re already starting to support the production ramp for ST. They’ll be on the market very soon.
[[Editor’s note: ST has announced three set-top box chips on 28nm FD-SOI– you can read about them here.]]
KL: Everyone’s waiting for ChipWorks or TechInsights to cut away an end-product device that has FD-SOI. It’s just a matter of time.
~ ~ ~
Synopsys has announced a comprehensive RTL-to-GDSII solution for GlobalFoundries 22nm technology process. The implementation and signoff tools from the Synopsys Galaxy™ Design Platform have been enabled for the current version of GF’s’ 22FDX™ platform reference flow. GF has qualified these tools to use body bias to manage power, performance and leakage to achieve optimal energy efficiency and cost effectiveness. (See the press release here.)
The Galaxy Design Platform supports body biasing techniques throughout the design flow, key to achieving optimal power and performance when using the 22FDX technology. Both forward body bias and reverse body bias are supported, enabling power/performance trade-offs to be made dynamically and delivering up to 50% power reduction.
The reference flow using the Galaxy Design Platform is now available for early customer engagement.
The recent LetiDays FD-SOI workshop in Grenoble was the biggest show of force to date for the burgeoning FD-SOI ecosystem. In addition to a raft of excellent presentations, we learned two very big pieces of news. First, GlobalFoundries provided more insights into their upcoming FD-SOI offering. And second, designers opting for Samsung’s 28nm FD-SOI offering can get all their IP (with Samsung numbering) directly from (and supported by) Synopsys.
In fact the workshop marked the first time that the entire ecosystem took to the same stage. It was great. Here’s a recap.
Although not “officially” announced yet, GlobalFoundries was there to talk about their FD-SOI offering. In his presentation on Design/Technology Opimizations for FD-SOI, Gerde Teepe, Design Enablement Director at GF in Dresden, said theirs would be 22nm FD-SOI. That translates to a 14nm front-end with two double-patterning layers, and 28nm upper interconnect layers in the back-end. Currently working on body-biasing generators, they’re on target to be completely ready for business by the end of the year (see slide below).
The decision to go with a 14nm front-end was customer driven, said Dr. Teepe. They wanted a shrink, but they didn’t want to drive up the cost, hence the 28nm back-end.
The conference made clear that there’s no more “chicken-egg” IP problem for FD-SOI. IP is ready, and everyone wants to talk about it.
Kelvin Low, Senior Director of Foundry Marketing at Samsung said they’re driving 28nm FD-SOI to get “massive support” for the ecosystem. It’s positioned as cost-effective, low-power solution for a long-lived node, he said, and yes, they’re getting new customers. Wafer level reliability tests were successfully completed last September, and product level reliability tests finished up in March.
This set the stage for the big IP news from Synopsys. Senior Director Mike McAweeney said that Synopsys is supplying both ST’s IP plus their own Synopsys IP to Samsung customers, with Samsung part numbers and Synopsys support.
IP is hot at Cadence, too, said Amir Bar-Niv, Senior Group Director for Design IP Marketing. Since February they’ve doubled the number of available IP to meet customer demand.
Proof of rising demand also came from CMP, which organizes multi-project wafer runs for 28nm FD-SOI. Over 191 customers in 32 countries have requested the PDK. (Click here to learn more about the service.)
New approaches to body biasing were mentioned in a number of presentations, including talks by ST, GF and Leti. GF’s working on their body-biasing generator for 22nm. ST’s got a new-generation compact body bias generator especially for IoT. And ST and Leti are working on a new generation of “adaptive” body biasing, adding another 30% in power savings.
In a very interesting keynote, Professor Boris Thurmann of Stanford looked at mixed-signal IC design. We’re about to fuse the physical and virtual worlds, he said, in a third paradigm: IoT. He cited lots of advantages of FD-SOI in meeting the ultra-low-power and RF challenges faced by analog designers.
FD-SOI attacks variability with tighter process corners and less random mismatch than competing processes. It enables “…a simpler design process, shorter design cycles, improved yield or improved performance at given yield”. You get outstanding switch performance (see slide) and better ways of dealing with junction capacitance.
FD-SOI renders a shift in RF to translational circuits (no inductors) more practical. It also enables smaller but higher performance digital blocks in apps for things like object recognition – and the list goes on.
Naim Ben-Hmida, Senior Manager of Mixed-Signal Design & Test at Ciena (they used to be Nortel), talked about optical transceivers in 28nm FD-SOI. We’re heading towards terabyte modems connecting cities, he said, putting enormous pressure on short-reach optical networks. Their 100Gb/s metro-regional transceiver integrates what was two ASICs and an FPGA into a single 28nm FD-SOI transceiver ASIC. In addition to power and performance, FD-SOI was the right solution for both time-to-market and cost, he said.
In closing, let’s swing back to the conference opening keynote by Thomas Skotnicki, ST’s FD-SOI godfather (you can also read his 2011 ASN piece on FD-SOI here). The key to the FD-SOI success story, he reminded us, is the thin buried oxide. That’s been the essence of his work for the last 26 years.
“You must believe in what you’re doing,” he said. Proof of his perseverence: his breakthrough paper was twice rejected by the IEEE in 1999 – but once they accepted it in 2000, they named it best paper of the year.
He gave a big thank you to Soitec for breakthroughs in SOI wafer manufacturing – the ultra-thin silicon and ultra-thin insulating BoX combination were the enabling tour-de-force.
Skotnicki added that for 14nm Soitec has taken the wafers to new heights. “At 14nm, we are very robust,” he concluded, noting that the Leti/ST VLSI Symposium 2015 (O. Faynot et al) paper showed 14nm FD-SOI matching or beating 14nm FinFET performance at low voltages. The future is wide open. FD-SOI, he says can go down to 5nm (compared to 3nm for FinFET).
And clearly, he’s a man who knows the future.
Synopsys recently announce that its IC Compiler II place and route solution was used by STMicroelectronics to tape out a complex 28-nm-FD-SOI SoC. (Read the press release here.) Fast throughput and analysis delivered a 10X reduction in time-to-good-floorplan. A 5X faster implementation with 2X smaller memory footprint enabled breakthrough productivity while exceeding quality of results (QoR) in area, timing and power goals.
Thierry Bauchon, ST R&D Director, said, “Our experience proved the promise we saw early in the design with 10X faster design exploration and 5X faster implementation, enabling us to refine floorplans, up-size physical partitions and achieve faster clock speeds on this tapeout.”