Tag Archive TSV

Leti’s M3D, now dubbed “CoolCube”, featured in EETimes

Leti's M3D technology is now called "CoolCube". (Courtesy: Leti, IEDM 2014)

Leti’s M3D technology is now called “CoolCube”. (Courtesy: Leti, IEDM 2014)

Leti’s monolithic 3D technology, which has now been dubbed “CoolCube”, was featured in a recent EETimes piece.  Entitled True 3D monolithic integration eliminates TSV dependence (click here to read it), the article covers a Leti paper presented during a 3D-VLSI workshop preceding IEDM ’14.  Leti’s Advanced CMOS lab manager Maud Vinet detailed the “cool” process in an FPGA, stacking a 14nm FD-SOI logic layer on top of a memory layer. It eliminates the need for TSVs, shrinks area by 55%, cut power in half and increases speed by 30%, effectively gaining a full node in terms of power and performance.

Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct)

S3Sheader

(For best rates, register by September 18th.)

The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco.

Photo Credit: Catherine Allibert

Photo Credit: Catherine Allibert

Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S conference was successful by any measurement. The first year of the new conference leading-edge experts from 3D Integration, Sub-threshold Microelectronics and SOI fields gathered and we established a world class international venue to present, learn and debate about these exciting topics. The overall participation at the first year of the new conference grew by over 50%, and the overall quality and quantity of the technical content grew even more.

This year we are looking forward to continuing to enhance the content of the 2014 S3S Conference.

 

Short courses: Monolithic 3D & Power-Efficient Chip Tech

On Monday, Oct. 6 we will feature two Short Courses that will run in parallel. Short courses are an educational venue where newcomers can gain overview and generalists can learn more details about new and timely topics.

The short course on Monolithic 3D will be a full day deep dive into the topic of three-dimensional integration wherein the vertical connectivity is compatible with the horizontal connectivity (10,000x better than TSV). Already there are extremely successful examples of monolithic 3D Flash Memory. Looking beyond this initial application, we will explore the application of monolithic 3D to alternate memories like RRAM, CMOS systems with silicon and other channel materials like III V. In addition, a significant portion of the short course will be dedicated to the exciting opportunity of Monolithic 3D in the context of CMOS Logic.

The other short course we will offer this year is entitled Power Efficient Chip Technology. This short course will address several key aspects of power-efficiency including low power transistors and circuits. The course will also review in detail the impact of design and architecture on the energy-efficiency of systems. The short course chairs as well as the instructors are world class leading experts from the most prestigious industry and academic institutions.

 

Conference program

The regular conference sessions will start on Tuesday Oct. 7 with the plenary session, which will feature presentations from Wall Street (Morgan Stanley Investment Banking), Microsoft and MediaTek. After the plenary session we will hear invited talks and this year’s selection of outstanding papers from international researchers from top companies and universities. The most up to date results will be shared. Audience questions and one on one interaction with presenters is encouraged.

Back by popular demand we will have 2 Hot Topics Sessions this year. The first Hot Topic Session is scheduled for Tuesday Oct. 7th and will feature exciting 3DI topics. The other Hot Topics session is scheduled for Thursday Oct 9 and will showcase new and exciting work in the area of MEMS.

Our unique poster session and reception format will have a short presentation by the authors followed by one on one interaction to review details of the poster with the audience, in a friendly atmosphere, around a drink. Last year we had regular posters as well as several invited posters with very high quality content and we anticipate this year’s poster session to be even better than last years.

We are offering a choice of two different fundamentals classes on Wednesday afternoon. One of the Fundamentals classes will focus on Robust Design of Subthreshold Digital and Mixed Circuits, with tutorials by the worlds leading experts in this field. The SOI fundamentals course is focused on RF SOI Technology Fundamentals and Applications.

Our technical content is detailed on our program webpage.

 

Panel discussions, cookout & more

Keeping in line with tradition, on Wednesday night we will have a hearty cook out with delicious food and drink followed by the Panel Session entitled Cost and Benefit of Scaling Beyond 14nm. Panel speakers from financial, semiconductor equipment, technology, and academic research institutions will gather along with the audience to debate this timely topic. Although Thursday is the last day of the conference we will have stimulating presentations on novel devices, energy harvesting, radiation effects along with the MEMS Hot Topic Session and Late News Session. As always we will finish the conference with the award ceremony for the best papers.

SFstreetsignOur conference has a long tradition of attracting presenters and audience members from the most prestigious research, technology and academic institutions from around the world. There are many social events at the S3S Conference as well as quiet time where ideas are discussed and challenged off line and people from various fields can learn more about other fields of interest from leading experts.

The conference also offers many opportunities for networking with people inside and also outside ones area. The venue this year is San Francisco. We chose this location to attract the regions leading experts from Academia and Industry. If you have free time we encourage you to explore San Francisco which is famous for a multitude of cultural and culinary opportunities.

Please take a moment to learn more about our conference by browsing our website or downloading our advance program.

To take full advantage of this outstanding event, register before September 18!

Special hotel rates are also available from the dedicated hotel registration page.

The committee and I look forward to seeing you in San Fransisco.

– Bruce Doris, S3S General Chair

 Photo Credit: Catherine Allibert

Photo Credit: Catherine Allibert

U. Washington Selects Altatech (Soitec) CVD System to Develop New Process Materials

Sans titre

The University of Washington’s Nanofabrication Facility (WNF) is the first North American institution to get an AltaCVD™ chemical vapor deposition (CVD) system (press release here). The AltaCVD system uses pulsed deposition technology to offer a unique combination of capabilities for developing new materials. It can perform atomic layer deposition (ALD) for exceptional 3D coverage at deposition rates matching those of more conventional CVD techniques. The system will be used by both internal and external researchers in fabricating a broad range of semiconductor-based devices including leading-edge CMOS transistors, MEMS, ICs built with the latest in through-silicon-via (TSV) technology, advanced LEDs and solar cells. Altatech is a subsidiary of Soitec (the world leader in SOI wafer manufacturing). AltaCVD systems have been used extensively in R&D and pilot production facilities throughout Europe; however, the University of Washington’s order represents the first such system to be delivered to a North American university R&D and pilot production facility.

Dr. Michael Khbeis, acting director of the WNF, said, “The AltaCVD system provides a unique capability that enables researchers to deposit conformal metal films for TSV applications as well as metal oxides and nitrides for high-k dielectrics and piezoelectric materials. The higher deposition rate enabled by pulsed CVD makes ALD films a tractable solution for scale-up paths toward high-volume manufacturing for our researchers and industrial clients. This ensures a viable pathway from academia to real economic impact in our region.”

SOI for MEMS: A Promising Material

A new Yole report highlights growth of SOI MEM S.

Although MEMS technologies are not driven by CD shrinking as ICs, that does not mean MEMS do not undergo strong technological evolutions. The ever-growing MEMS markets, today mostly driven by consumer applications, now have to be performance-driven, cost-driven and size driven.

SOI wafers are a promising substrate for MEMS manufacturing. We estimate the SOI market for MEMS devices will be close to $100M by 2015 (see Figure 1).   That represents a CAGR (2011-2015) of 15.6% for SOI, compared to 8.1% for bulk silicon-based solutions.

 

Figure 1: Substrate Market for MEMS

One main reason for using SOI is to have more design freedom. Tronics, for example is using SOI with High Aspect Ratio Micromachining technology. This technology was developed to manufacture high performance custom inertial sensors (accelerometers and gyroscopes).

Other reasons cited for choosing an SOI-based solution for MEMS include the need for the smallest possible package, very tight control and precision of the structure, ability to withstand high pressure and temperature, long product lifetime, smallest possible die size and reduced cost.

Additional features in SOI wafers can further simplify MEMS design and manufacturing. For example, “cavity-SOI”, in which the SOI wafer has pre-etched cavities, enables the MEMS manufacturers to focus on their core competencies in reducing development time, which in turn can even lower production costs. Some MEMS manufacturers have found that pre-etched SOI cavities combined with dry etching simplifies the release of the devices.

MEMS manufacturers using cavity-SOI include VTI Technologies, Invensense and other players in the seismic accelerometer (Tronics)  and pressure sensor markets.

Figure 2 shows a roadmap for SOI wafers for MEMS. From “traditional” SOI, we are now using SOI with pre-etched cavities. Further developments will allow the realization of SOI wafers with trench isolation, cavities and Through Silicon Vias (TSV).

Suppliers of other substrate solutions are following similar added-value paths. Glass, for example, can be used as a thin wafer carrier for wafer level capping and/or packaging with Through Glass Vias interconnect.

Overall, we believe substrates will  provide additional functionalities in the future, enabling more integrated MEMS devices.

 

Figure 2: Roadmap for SOI Wafers for MEMS

The information in this article is taken from the Yole Report “Trends in MEMS Manufacturing & Packaging”. Contact Yole Development for more information about  reports and services.

SOI at IEDM 2010

The 2010 IEEE International Electron Devices Meeting (IEDM) was held December 6-8, 2010 in San Francisco. The IEDM continues to be the world’s premier venue for presenting the latest breakthroughs and the broadest and best technical information in electronic device technologies.

Here are summaries of key papers referencing work on SOI or other advanced substrates.

(Note: at the time of this posting, the papers are not yet available from the  IEEE Xplore website.  However, many are available from the Advanced Silicon Device and Process Lab at the National Taiwan University.)


Paper #1.2: Energy Efficiency Enabled by Power Electronics
Arunjai Mittal (Infineon)

In particular, see section 4, where the author addresses the huge energy savings that can be realized using variable speed motors. Infineon’s driver ICs (which take a logic signal output from a microcontroller chip in the control system, and provide the appropriate current and voltage to turn power devices on and off) are built on SOI. (See Infineon’s article in ASN7. Infineon and LS Industrial Systems started a JV in 2009 called the LS Power Semitech Co., which leverages this technology.)


#2.6: Engineered Substrates and 3D Integration Technology Based on Direct Bonding for Future More Moore and More than Moore Integrated Devices (Invited)

L. Clavelier, C. Deguet, L. Di Cioccio, E. Augendre, A. Brugere, P. Gueguen, Y Le Tiec, H. Moriceau, M. Rabarot, T. Signamarcheix, J. Widiez, O. Faynot, F. Andrieu, O. Weber, C. Le Royer, P. Batude, L. Hutin, J.F. Damlencourt, S. Deleonibus, E. Defaÿ, (CEA/LETI Minatec)

This paper deals with new generations of substrates and 3D integration techniques, based on direct bonding techniques, enabling future devices in the More Moore and in the More than Moore areas.


#3.2 : Planar Fully Depleted SOI Technology: A Powerful Architecture for the 20nm Node and Beyond (Invited)

O. Faynot, F. Andrieu, O. Weber, C. Fenouillet-Béranger, P. Perreau, J. Mazurier, T. Benoist, O. Rozeau, T. Poiroux, M. Vinet, L. Grenouillet, J-P. Noel, N. Posseme, S. Barnola, F. Martin, C. Lapeyre, M. Cassé, X. Garros, M-A. Jaud, O. Thomas, G. Cibrario, L. Tosti, L. Brévard, C. Tabone, P. Gaud, S. Barraud, T. Ernst and S. Deleonibus (CEA/LETI Minatec)

The authors of this paper say that for 20nm node and below, they have proven that planar undoped channel Fully Depleted SOI devices are easier to integrate than bulk, non planar devices like FinFET. The paper gives an overview of the main advantages provided by this technology, as well as the key challenges that need to be addressed.


#3.3:  Anomalous Electron Mobility in Extremely-Thin SOI (ETSOI) Diffusion Layers with SOI Thickness of Less Than 10 nm and High Doping Concentration of Greater Than 1x1018cm-3

N. Kadotani,T. Takahashi, K. Chen,T. Kodera, S. Oda, K. Uchida*  (Tokyo Institute of Technology, *also with PRESTO)

This paper is the first to report carrier transport in heavily doped ETSOI diffusion layers. The authors found that electron mobility in the heavily doped ETSOI diffusion layer is totally different from electron mobility in heavily doped bulk Si. In other words, electron mobility is enhanced in thinner ETSOI diffusion layers (Tsoi>5nm), whereas electron mobility is degraded as dopant concentration increases when Tsoi is 2nm. The authors conclude that this information will be indispensable for the design of aggressively scaled ETSOI devices as well as 3D FETs.


#3.4:  Work-function Engineering in Gate First Technology for Multi-VT Dual-Gate FDSOI CMOS on UTBOX

O. Weber, F. Andrieu, J. Mazurier, M. Cassé, X. Garros, C. Leroux, F. Martin, P. Perreau, C. Fenouillet-Béranger, S. Barnola, R. Gassilloud, C. Arvet*, O. Thomas, J-P. Noel, O. Rozeau, M-A. Jaud, T. Poiroux, D. Lafond, A. Toffoli, F. Allain, C. Tabone, L. Tosti, L. Brévard, P. Lehnen #, U. Weber#, P.K. Baumann#, O. Boissiere#, W. Schwarzenbach+, K. Bourdelle+, B-Y Nguyen+, F. Boeuf*, T. Skotnicki*, and O. Faynot (CEA-LETI Minatec, *STMicroelectronics, #AIXTRON AG, +SOITEC)

For the first time, the authors demonstrate low-VT (VTlin ~± 0.32) nMOS and pMOS adjusted in a gate first FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for low-VT pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune the work-function above midgap while maintaining good reliability and mobility. Short channel performance of 500μA/μm ION and 245μA/μm IEFF at 2nA/μm IOFF and VDD=0.9V is reported on pMOS with a TaAlN gate. In addition, it is found that the combination of these two metal gates with either n- or p-doped ground planes below the Ultra-Thin Buried Oxide (BOX) can offer 4 different VT from 0.32V to 0.6V for both nMOS and pMOS.


#8.1: Compact Modeling and Analysis of Coupling Noise Induced by Through-Silicon Vias in 3-D ICs

C. Xu, R. Suaya*, K. Banerjee (UC Santa Barbara, *Mentor Graphics)

This work presents compact models for cases without and with the high conductivity buried layer in dual-well bulk CMOS, which can be employed for keep away radius estimation. A comparative analysis of the coupling noise due to TSV in both dual-well bulk CMOS and PD-SOI is presented. The noise coupling for PD-SOI is much smaller than that of bulk CMOS due to the significantly shorter TSV height compared to that in bulk CMOS.


#8.2:  Large Signal Substrate Modeling in RF SOI Technologies

S. Parthasarathy, B. Swaminathan, A. Sundaram, R.A. Groves, R.L. Wolf, F.G. Anderson (IBM SRDC)

This paper describes a large signal high resistivity (HR) SOI substrate modeling methodology for high power circuit applications such as RF switches.  The authors show that using a varactor to model the BOX capacitor improves the harmonic distortion predictions from simulations for circuits in RF/Analog applications.


#8.5: MuGFET Carrier Mobility and Velocity: Impacts of Fin Aspect Ratio, Orientation and Stress

N. Xu, X. Sun, W. Xiong*, C. R. Cleavelin, T.-J. King Liu (UC Berkeley, *Texas Instruments)

The authors made a detailed study of the impacts of fin aspect ratio and crystalline orientation and process-induced channel stress on the performance of multi-gate transistors. The MuGFETs studied in this work were fabricated on (100) SOI substrates, with either <100> or <110> fin orientation.  They found that CESL-induced stress provides for the greatest enhancement in carrier mobility and ballistic velocity, for n- and p-channel FinFETs and Tri-Gate FET structures. Extracted carrier velocity values in short-channel FinFETs still largely depend on carrier mobility.


#11.1:  Dual Strained Channel Co-Integration into CMOS, RO and SRAM Cells on FDSOI Down to 17nm Gate Length

L. Hutin, C. Le Royer, F. Andrieu, O. Weber, M. Cassé, J.-M. Hartmann, D. Cooper, A. Béché*, L. Brevard, L. Brunet, J. Cluzel, P. Batude, M. Vinet, O. Faynot (CEA LETI Minatec, CEA-INAC)

The authors presented the first successful Dual Strained Channel On Insulator (DSCOI) planar co-integration of tensily strained SOI nFETs and compressively strained SiGeOI pFETs down to 17nm gate length with functional ring oscillators and 6T SRAM cells.  Strained SiGe channels were found to present up to 92% long channel mobility improvement (Eeff=0.6MV/cm); the asset of effective mass reduction is highlighted for short channel pFETs. Moreover, the co-integration with sSOI nFETs leads to well-adjusted Vth,n and Vth,p with a single mid-gap gate for high performance applications, as shown by a 39% improvement of the ring oscillators propagation delay compared to the SOI reference.


#11.2: A Solution for an Ideal Planar Multi-Gates Process for Ultimate CMOS?

S. Monfray, J.-L. Huguenin, M. Martin*, M.-P. Samson, C. Borowiak, C. Arvet, JF. Dalemcourt*, P. Perreau*, S. Barnola*, G. Bidal, S. Denorme, Y. Campidelli, K. Benotmane*, F. Leverd, P. Gouraud, B. Le-Gratiet, C. De-Butet*, L. Pinzelli, R. Beneyton, T. Morel, R.Wacquez*, J. Bustos, B. Icard*, L. Pain*, S. Barraud*, T. Ernst*, F. Boeuf, O. Faynot*, T. Skotnicki (STMicroelectronics, *CEA LETI Minatec)

The authors demonstrate for the first time high-performant planar multi-gates devices integrated on an SOI substrate, with Si-conduction channel of 4nm, allowing drive current up to 1350μA/μm @Ioff=0.4nA/μm. They also demonstrate an ideal planar self-aligned solution, based on the direct exposure of a HSQ layer through a 5nm Si-channel. This opens the way to an easy planar multi-gate process for ultimate CMOS (11nm node & below), fully co-integrable with conventional devices.


#12.1: 32nm High-density High-speed T-RAM Embedded Memory Technology

R. Gupta, F. Nemati, S. Robins, K. Yang, V. Gopalakrishnan, J.J. Sundarraj, R. Chopra, R. Roy, H.-J. Cho*, W.P. Maszara*, N.R. Mohapatra*, J. Wuu**, D. Weiss**, S. Nakib (T-RAM Semiconductor, *GLOBALFOUNDRIES, **AMD)

The authors present Thyristor Random Access Memory (T-RAM) as an ideal candidate for embedded memory due to its substantially better density-performance and logic process compatibility.  T-RAM technology with substantially better density-performance tradeoff  was previously reported was previously reported at the 130nm technology node. This paper is the first to report implementation details in a 32nm HKMG SOI CMOS logic process, with read and write times of 1ns and bit fail rate under 0.5ppm.


#12.3:  A Novel Low-Voltage Biasing Scheme for Double Gate FBC Achieving 5s Retention and 1016 Endurance at 85ºC

Z. Lu, N. Collaert, M. Aoulaiche, B. De Wachter, A. De Keersgieter, W. Schwarzenbach*, O. Bonnin*, K. K. Bourdelle*, B.-Y. Nguyen**, C. Mazure*, L. Altimime, M. Jurczak (IMEC, *SOITEC, **SOITEC-USA)

A novel low-voltage biasing scheme on ultra-thin BOX FDSOI floating body cell is experimentally demonstrated. The new biasing scheme enhances the positive feedback loop. Therefore, the required VDS can be reduced to 1.5V while 5 seconds retention time can still be achieved at 85oC. Endurance up to 1016 cycles is shown.


#16.6: Realizing Super-Steep Subthreshold Slope with Conventional FDSOI CMOS at Low-Bias Voltages (Late News)

Z. Lu*#, N. Collaert*, M. Aoulaiche*, B. De Wachter*, A. De Keersgieter*, J. Fossum#, L. Altimime*, M. Jurczak* (*IMEC, #U. Florida/Gainesville)

The authors report the first experimental demonstration of a super-steep subthreshold slope (the smallest ever reported experimentally) with ultra-thin BOX FDSOI standard CMOS transistors. This work addresses the scaling challenge of continuing to reduce power consumption by lowering operation voltage.  Record steep SS of 72μV/dec for Lg=25nm and 58μV/dec for Lg=55nm are achieved with low voltages. The device also exhibits high ION (~100μA/μm), large ION/IOFF ratio of 108 with 0.5V gate swing for Lg=55nm MOSFETs and excellent reliability.


#18.3: Prospects for MEM Logic Switch Technology (Invited), T.-J. King Liu, J. Jeon, R. Nathanael, H. Kam, V. Pott*, E. Alon (UC Berkeley, *Institute of Microelectronics/Singapore)

This paper provides an overview of recent progress in device design, materials/process integration and technology scaling toward achieving micro-electro-mechanical  (MEM) switches suitable for ultra-low-power digital IC applications.


#27.5: A 0.039um2 High Performance eDRAM Cell Based on 32nm High-K/Metal SOI Technology

N. Butt, K. Mcstay, A. Cestero, H. Ho, W. Kong, S. Fang, R. Krishnan, B. Khan, A. Tessier, W. Davies, S. Lee, Y. Zhang, J. Johnson, S. Rombawa, R. Takalkar, A. Blauberg, K.V. Hawkins, J. Liu, S. Rosenblatt, P. Goyal, S. Gupta, J. Ervin, Z. Li, S. Galis, J. Barth, M. Yin, T. Weaver, J. H. Li, S. Narasimha, P. Parries, W.K. Henson, N. Robson, T. Kirahata, M. Chudzik, E. Maciejewski, P. Agnello, S. Stiffler, and S.S. Iyer (IBM SRDC)

The authors present the industry’s smallest eDRAM cell and the densest embedded memory integrated into the highest performance 32nm High-K Metal Gate SOI based logic technology. With aggressive cell scaling, High-K/Metal trench lowers parasitic resistance while maximizing capacitance. Fully-integrated 32Mb product prototypes demonstrate state-of-the-art sub 1.5ns latency with excellent retention and yield characteristics. The sub 1.5ns latency and 2ns cycle time have been verified with preliminary testing whereas even better performance is expected with further characterization. In addition, the trench capacitors set the industry benchmark for the most efficient decoupling in any 32nm technology.


#34.2:  Strained SiGe and Si FinFETs for High Performance Logic with SiGe/Si Stack on SOI

I. Ok, K. Akarvardar*, S. Lin**, M. Baykan^, C.D. Young, P.Y. Hung, M.P. Rodgers^^, S. Bennett^^, H.O. Stamper^^, D.L. Franca^^, J. Yum#, J.P. Nadeau##, C. Hobbs, P. Kirsch, P. Majhi, R. Jammy (SEMATECH, *GLOBALFOUNDRIES, **UMC, ^U.Florida, ^^CNSE, #U. Texas/ Austin, ##FEI)

The authors have demonstrated high performance p-channel Si/SiGe stacked FinFETs with salient features including 1) high intrinsic mobility; 2) good interface quality without the need for a Si cap between SiGe and High-k; 3) low series resistance; 4) process-induced strain additivity; and 5) a convenient threshold voltage for high performance logic using a midgap metal gate. They also demonstrate a dual channel scheme for high mobility CMOS FinFETs.


#34.3: Understanding of Short-Channel Mobility in Tri-Gate Nanowire MOSFETs and Enhanced Stress Memorization Technique for Performance Improvement

M. Saitoh, Y. Nakabayashi, K. Ota, K. Uchida*, and T. Numata (Toshiba Corp., *Tokyo Institute of Technology)

The authors found that short-channel mobility in SOI nanowire transistors (NW Tr.) is dominated by the strain induced in the NW channel. They enhanced NW strain by the stress memorization technique (SMT). In <110> NW nFETs, Ion on the same DIBL largely increases by SMT thanks to mobility increase and parasitic resistance reduction.  They conclude that stress engineering is highly effective for the performance improvement of scaled NW Tr.


#34.5:  Investigation of Hole Mobility in Gate-All-Around Si Nanowire p-MOSFETs with High-k/Metal-Gate: Effects of Hydrogen Thermal Annealing and Nanowire Shape

P. Hashemi, J.T. Teherani, J.L. Hoyt (MIT Microsystems Technology Laboratories)

The authors present a detailed study of hole mobility for gate-all-around Si NW p-MOSFETs with conformal high-k/MG and various hydrogen annealing processes. The devices are fabricated along the <110> direction on (100) thin body SOI.  Increasing hole mobility is observed with decreasing NW width down to 12 nm. A 33% hole mobility enhancement is achieved relative to universal (100) at high Ninv.


#35.4:  A Quantitative Inquisition into ESD Sensitivity to Strain in Nanoscale CMOS Protection Devices

D.Sarkar, S. Thijs*, D. Linten*, C. Russ**, H. Gossner**, K. Banerjee, (UC Santa Barbara, *IMEC, **Infineon Technologies)

The authors investigated the impact of strain on different ESD protection devices. It is shown for the first time that the ESD sensitivity to strain can vary substantially depending on whether the devices stressed are bulk or SOI and on the mode in which they are stressed.  investigated. SOI NMOS exhibits about 20% improvement in ESD robustness in GG mode. The authors conclude that strain will play an important role in optimization of ESD device robustness of advanced CMOS technologies.