Leti’s monolithic 3D technology, which has now been dubbed “CoolCube”, was featured in a recent EETimes piece. Entitled True 3D monolithic integration eliminates TSV dependence (click here to read it), the article covers a Leti paper presented during a 3D-VLSI workshop preceding IEDM ’14. Leti’s Advanced CMOS lab manager Maud Vinet detailed the “cool” process in an FPGA, stacking a 14nm FD-SOI logic layer on top of a memory layer. It eliminates the need for TSVs, shrinks area by 55%, cut power in half and increases speed by 30%, effectively gaining a full node in terms of power and performance.
The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco.
Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S conference was successful by any measurement. The first year of the new conference leading-edge experts from 3D Integration, Sub-threshold Microelectronics and SOI fields gathered and we established a world class international venue to present, learn and debate about these exciting topics. The overall participation at the first year of the new conference grew by over 50%, and the overall quality and quantity of the technical content grew even more.
This year we are looking forward to continuing to enhance the content of the 2014 S3S Conference.
Short courses: Monolithic 3D & Power-Efficient Chip Tech
On Monday, Oct. 6 we will feature two Short Courses that will run in parallel. Short courses are an educational venue where newcomers can gain overview and generalists can learn more details about new and timely topics.
The short course on Monolithic 3D will be a full day deep dive into the topic of three-dimensional integration wherein the vertical connectivity is compatible with the horizontal connectivity (10,000x better than TSV). Already there are extremely successful examples of monolithic 3D Flash Memory. Looking beyond this initial application, we will explore the application of monolithic 3D to alternate memories like RRAM, CMOS systems with silicon and other channel materials like III V. In addition, a significant portion of the short course will be dedicated to the exciting opportunity of Monolithic 3D in the context of CMOS Logic.
The other short course we will offer this year is entitled Power Efficient Chip Technology. This short course will address several key aspects of power-efficiency including low power transistors and circuits. The course will also review in detail the impact of design and architecture on the energy-efficiency of systems. The short course chairs as well as the instructors are world class leading experts from the most prestigious industry and academic institutions.
The regular conference sessions will start on Tuesday Oct. 7 with the plenary session, which will feature presentations from Wall Street (Morgan Stanley Investment Banking), Microsoft and MediaTek. After the plenary session we will hear invited talks and this year’s selection of outstanding papers from international researchers from top companies and universities. The most up to date results will be shared. Audience questions and one on one interaction with presenters is encouraged.
Back by popular demand we will have 2 Hot Topics Sessions this year. The first Hot Topic Session is scheduled for Tuesday Oct. 7th and will feature exciting 3DI topics. The other Hot Topics session is scheduled for Thursday Oct 9 and will showcase new and exciting work in the area of MEMS.
Our unique poster session and reception format will have a short presentation by the authors followed by one on one interaction to review details of the poster with the audience, in a friendly atmosphere, around a drink. Last year we had regular posters as well as several invited posters with very high quality content and we anticipate this year’s poster session to be even better than last years.
We are offering a choice of two different fundamentals classes on Wednesday afternoon. One of the Fundamentals classes will focus on Robust Design of Subthreshold Digital and Mixed Circuits, with tutorials by the worlds leading experts in this field. The SOI fundamentals course is focused on RF SOI Technology Fundamentals and Applications.
Our technical content is detailed on our program webpage.
Panel discussions, cookout & more
Keeping in line with tradition, on Wednesday night we will have a hearty cook out with delicious food and drink followed by the Panel Session entitled Cost and Benefit of Scaling Beyond 14nm. Panel speakers from financial, semiconductor equipment, technology, and academic research institutions will gather along with the audience to debate this timely topic. Although Thursday is the last day of the conference we will have stimulating presentations on novel devices, energy harvesting, radiation effects along with the MEMS Hot Topic Session and Late News Session. As always we will finish the conference with the award ceremony for the best papers.
Our conference has a long tradition of attracting presenters and audience members from the most prestigious research, technology and academic institutions from around the world. There are many social events at the S3S Conference as well as quiet time where ideas are discussed and challenged off line and people from various fields can learn more about other fields of interest from leading experts.
The conference also offers many opportunities for networking with people inside and also outside ones area. The venue this year is San Francisco. We chose this location to attract the regions leading experts from Academia and Industry. If you have free time we encourage you to explore San Francisco which is famous for a multitude of cultural and culinary opportunities.
To take full advantage of this outstanding event, register before September 18!
Special hotel rates are also available from the dedicated hotel registration page.
The committee and I look forward to seeing you in San Fransisco.
– Bruce Doris, S3S General Chair
The University of Washington’s Nanofabrication Facility (WNF) is the first North American institution to get an AltaCVD™ chemical vapor deposition (CVD) system (press release here). The AltaCVD system uses pulsed deposition technology to offer a unique combination of capabilities for developing new materials. It can perform atomic layer deposition (ALD) for exceptional 3D coverage at deposition rates matching those of more conventional CVD techniques. The system will be used by both internal and external researchers in fabricating a broad range of semiconductor-based devices including leading-edge CMOS transistors, MEMS, ICs built with the latest in through-silicon-via (TSV) technology, advanced LEDs and solar cells. Altatech is a subsidiary of Soitec (the world leader in SOI wafer manufacturing). AltaCVD systems have been used extensively in R&D and pilot production facilities throughout Europe; however, the University of Washington’s order represents the first such system to be delivered to a North American university R&D and pilot production facility.
Dr. Michael Khbeis, acting director of the WNF, said, “The AltaCVD system provides a unique capability that enables researchers to deposit conformal metal films for TSV applications as well as metal oxides and nitrides for high-k dielectrics and piezoelectric materials. The higher deposition rate enabled by pulsed CVD makes ALD films a tractable solution for scale-up paths toward high-volume manufacturing for our researchers and industrial clients. This ensures a viable pathway from academia to real economic impact in our region.”
A new Yole report highlights growth of SOI MEM S.
Although MEMS technologies are not driven by CD shrinking as ICs, that does not mean MEMS do not undergo strong technological evolutions. The ever-growing MEMS markets, today mostly driven by consumer applications, now have to be performance-driven, cost-driven and size driven.
SOI wafers are a promising substrate for MEMS manufacturing. We estimate the SOI market for MEMS devices will be close to $100M by 2015 (see Figure 1). That represents a CAGR (2011-2015) of 15.6% for SOI, compared to 8.1% for bulk silicon-based solutions.
One main reason for using SOI is to have more design freedom. Tronics, for example is using SOI with High Aspect Ratio Micromachining technology. This technology was developed to manufacture high performance custom inertial sensors (accelerometers and gyroscopes).
Other reasons cited for choosing an SOI-based solution for MEMS include the need for the smallest possible package, very tight control and precision of the structure, ability to withstand high pressure and temperature, long product lifetime, smallest possible die size and reduced cost.
Additional features in SOI wafers can further simplify MEMS design and manufacturing. For example, “cavity-SOI”, in which the SOI wafer has pre-etched cavities, enables the MEMS manufacturers to focus on their core competencies in reducing development time, which in turn can even lower production costs. Some MEMS manufacturers have found that pre-etched SOI cavities combined with dry etching simplifies the release of the devices.
MEMS manufacturers using cavity-SOI include VTI Technologies, Invensense and other players in the seismic accelerometer (Tronics) and pressure sensor markets.
Figure 2 shows a roadmap for SOI wafers for MEMS. From “traditional” SOI, we are now using SOI with pre-etched cavities. Further developments will allow the realization of SOI wafers with trench isolation, cavities and Through Silicon Vias (TSV).
Suppliers of other substrate solutions are following similar added-value paths. Glass, for example, can be used as a thin wafer carrier for wafer level capping and/or packaging with Through Glass Vias interconnect.
Overall, we believe substrates will provide additional functionalities in the future, enabling more integrated MEMS devices.