Tag Archive UC Berkeley

ByAdele Hars

Silicon Valley FD-SOI 2018 Training Day is April 27th – Don’t Miss It!

Following the immense success of last years FD-SOI training day in Silicon Valley, the SOI Consortium has another one planned for the end of April this year. If you want to start learning how to leverage FD-SOI in your chip designs, this is a great place to start. Click here for information on how to sign up.

ST Fellow Dr. Andreia Cathelin has put together another great line-up. World renowned professors and experts from industry will deliver a series of four training sections of 1.5 hours each, focused on energy efficient and low-power, low-voltage design techniques for analog, RF, high-speed, mmW and mixed-signal design.

You’ll learn about design techniques that take full advantage of the unique features of FD-SOI, including body biasing capabilities that further enhance the excellent analog/RF performances of these devices.

Each section of this training day will take you through concrete design examples that illustrate new implementation techniques enabled by FD-SOI technologies at the 28nm and 22nm nodes – and beyond.

The design examples will cover basic building blocks through SoC implementations. A global Q&A session will close the day.

Here’s a little more info on how the day will unfold. Click on the slides to see them in full screen.

Morning sessions

FDSOI-specific design techniques for analog, RF and mmW applicationsAndreia Cathelin, Fellow, STMicroelectronics

Quick preview from Andreia Cathelin’s FD-SOI training session (Courtesy: STMicroelectronics, SOI Consortium)

Andreia Cathelin is ST’s key design scientist for all advanced CMOS technologies, and is arguably the world’s leading expert on leveraging FD-SOI in high-performance, low-power RF/AMS SoCs. Her course will first present a very short overview of the major analog and RF technology features of 28nm FDSOI technology. Then the focus moves to the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits. She’ll give design examples such as analog low-pass filters, inverter-based analog amplifiers and 30GHz and 60GHz Power Amplifiers, as well as mmW oscillators. There will be particular focus on the advantages of body biasing and special design techniques offering state-of-the-art performance.

Circuit Design Techniques in 22nm FD-SOI for 5G 28GHz ApplicationsFrank Zhang, Principal Member of Technical Staff, GlobalFoundries

Quick preview from Frank Zhang’s FD-SOI training session (Courtesy: GlobalFoundries, SOI Consortium)

Frank Zhang has designed chips using GF’s 22nm FD-SOI (22FDX) process for WLAN, 5G cellular and automotive radar applications. His course will focus on how to take advantages of FD-SOI’s high-frequency performance at relatively low-current density to design high performance RF/mmWave circuits. Examples circuits include a 28GHz LNA, a 28GHz PA and an RF switch for 5G applications. The FD-SOI advantages such as low capacitance, high breakdown voltage and high-output impedance will be exploited in these design examples. This course will also discuss how to extend these techniques to applications at higher frequencies and/or higher current densities that are subject to extreme temperatures and EM requirements.

Afternoon sessions

Energy-Efficient Design in FDSOIBora Nikolic, Professor, UC Berkeley

Quick preview from Bora Nikolić’s FD-SOI training session (Courtesy: UC Berkeley, SOI Consortium)

Borivoje (“Bora”) Nikolić is known as one of the world’s top experts in body-biasing for digital logic (he and his team have designed more than ten chips in ST’s 28nm FD-SOI.) If you missed it, his team’s RISC-V chip was cited as one of Dr. Cathelin’s “Outstanding 28nm FD-SOI Chips Taped Out Through CMP” – read more about that here. His talk at the training day will present options for energy-efficient mixed-signal and digital design in FD-SOI technologies. He’ll explain how to generate body bias and use it to improve efficiency, with examples in RF and baseband building blocks, temperature sensors, data converters and voltage regulators. The techniques will be presented in the context of UC Berkeley’s latest RISC-V-based SoC, designed to operate in a very wide voltage range using 28nm FD-SOI.

mm-Wave and Fiber-Optics Design in FD-SOI CMOS Technologies – Sorin Voinigescu, Professor, University of Toronto

Quick preview from Sorin Voinigescu’s FD-SOI training session (Courtesy: U. Toronto, SOI Consortium)

Sorin Voinigescu is a world renowned expert on millimeter-wave and 100+Gb/s ICs and atomic-scale semiconductor device technologies. His lecture will cover the main features of FD-SOI CMOS technology and how to efficiently use its unique features and suitable circuit topologies for mm-wave and broadband SoCs. He’ll begin with an overview of the impact of the back-gate bias and temperature on the measured I-V, transconductance, fT, and fMAX characteristics. Then he’ll compare the maximum available gain, MAG, of FDSOI MOSFETs with those of planar bulk CMOS and SiGe BiCMOS transistors through measurements up to 325 GHz. Next, he’ll provide biasing, sizing and step-by-step design examples for VCO, doubler, switches, PA, large swing optical modulator drivers and quasi-CML circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of 20nm and 12nm FD-SOI CMOS technologies.

Sign Up Now!

With over 100 attendees filling every chair in the auditorium, last year’s training day was sold out. Although it was in Silicon Valley, people actually flew in from all over the world to be there. During the Q&A at the end, most everyone prefaced their questions by saying, “Thank you. I really learned a lot today.”

2018 will be no different – except that it’s sure to sell out even faster. Please note, though, that this is not a free event, so only the attendees will get copies of the slide decks.

Here’s key info you need to sign up. See you there!

What: SOI Consortium’s FD-SOI Training Day

When: 27 April 2018, 7:30am – 5pm.

Where: Crowne Plaza San Jose, Milpitas CA (parking is free)

Registration fee: US $485.00 (includes training book, breakfast, box lunch and refreshments during breaks)

How to sign up: Click here to go directly to the registration site.

ByAdele Hars

Quick Preview of (Great!) FD-SOI Design Tutorial Day (14 April ’17, Silicon Valley)

Would you like to better understand FDSOI-based chip design? If you’re in Silicon Valley, you’re in luck. On April 14th, the SOI Consortium is organizing a full day of FDSOI tutorials for chip designers. This is not a sales day. This is a learning day.

On the agenda are FD-SOI specific design techniques for: analog and RF integration (millimeter wave to high-speed wireline), ultra-low-power memories and microprocessor architecture, and finally energy-efficient digital and analog-mixed signal processing designs.

The courses will be given by top professors at top universities (including UC Berkeley, Stanford, U. Toronto and Lund). These folks not only know FDSOI inside and out, they’ve all spent many years working closely with industry, so they truly understand the challenges designers face. They’ve helped design real (and impressive) chips, and have stories to tell. (In fact, all of the chips they’ll be presenting were included in CMP’s multiproject wafer runs – click here if you want to see and read about some of them on CMP website.)

The FD-SOI Tutorial Day, which will be held in San Jose, will begin at 8am and run until 3pm. Each professor’s course will last one hour. Click here for registration information.  

(The Tutorial Day follows the day after the annual SOI Silicon Valley Symposium in Santa Clara, which will be held on April 13th.)

Here’s a sneak peak at what the professors will be addressing during the FDSOI Tutorial Day.

FDSOI Short Overview and Advantages for Analog, RF and mmW Design – Andreia Cathelin, Fellow, STMicroelectronics, France

If you know anything about FDSOI, you know ST’s been doing it longer than pretty much than anyone. Professor Cathelin will share her deep experience in designing ground-breaking chips.

Summary slide from Professor Andreia Cathelin’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and ST)

She’ll start with a short overview of basic FDSOI design techniques and models, as well as the major analog and RF technology features of 28nm FDSOI technology.  Then the focus  shifts to the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits, considering the full advantages of wide-voltage range tuning through body biasing.  For each category of circuits  (analog/RF and mmW), she’ll show concrete design examples such as an analog low-pass  filter and a 60GHz Power Amplifier (an FDSOI-aware evolution of the one featured on the cover of Sedra/Smith’s Microelectronics Circuits 7th edition, which is probably on your bookshelf.) These will highlight the main design features specific to FD-SOI and offer silicon-proof of the resulting performance.

Unique Circuit Topologies and Back-gate Biasing Scheme for RF, Millimeter Wave and Broadband Circuit Design in FDSOI Technologies – Sorin Voinigescu, Professor, University of Toronto, Canada.

Particularly well-known for his work in millimeter wave and high-speed wireline design and modeling (which are central to IoT and 5G), Professor Voinigescu has worked with SOI-based technologies for over a decade. His course will cover how to efficiently use key features of FD-SOI CMOS technology in RF, mmW and broadband fiber-optic SoCs. He’ll first give an overview at the transistor level, presenting the impact of the back-gate bias on the measured I-V, transconductance, fT and fMAX characteristics.  The maximum available power gain (MAG) of FDSOI MOSFETs will be compared with planar bulk CMOS and SiGe BiCMOS transistors through measurements up to 325 GHz.

Summary slide from Professor Sorin Voinigescu’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and U. Toronto)

Next, he’ll provide design examples including LNA, mixer, switches, CML logic and PA circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of sub-28nm CMOS technologies. Finally, he’ll look at a 60Gb/s large swing driver in 28nm FDSOI CMOS for a large extinction-ratio 44Gb/s SiPh MZM 3D-integrated module, as a practical demonstration of the unique capabilities of FDSOI technologies that cannot be realized in FinFET or planar bulk CMOS.

Design Strategies for ULV memories in 28nm FDS-SOI – Joachim Rodrigues, Professor, Lund University, Sweden

Having started his career as a digital ASIC process lead in the mobile group at Ericsson, Professor Rodrigues has a deep understanding of ultra-low power requirements. His tutorial will examine two different design strategies for ultra-low voltage (ULV) memories in 28nm FD-SOI.

For small storage capacities (below 4kb), he’ll cover the design of standard-cell based memories (SCM), which is based on a custom latch. Trade-offs for area cost, leakage power, access time, and access energy will be examined using different read logic styles. He’ll show how the full custom latch is seamlessly integrated in an RTL-GDSII design flow.

Summary slide from Professor Joachim Rodrigues’ course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and Lund U.)

Next, he’ll cover the characteristics of a 28nm FD-SOI 128 kb ULV SRAM, based on a 7T bitcell with a single bitline. He’ll explain how the overall energy efficiency is enhanced by optimizations on all abstraction levels, from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address-decoding scheme delivers 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access. All performance data is silicon-proven.

Energy-Efficient Processors in 28nm FDSOI – Bora Nikolic, Professor, UC Berkeley, USA

Considered by his students at Berkeley as an “awesome” teacher, Professor Nikolic’s research activities include digital, analog and RF integrated circuit design and communications and signal processing systems. An expert in body-biasing, he’s now working on his 8th generation of energy-efficient SOCs. During the FDSOI tutorial, he’ll cover techniques specific to FDSOI design in detail, and present the design of a series of energy-efficient microprocessors. They are based on an open and free Berkeley RISC-V architecture and implement several techniques for operation in a very wide voltage range utilizing 28nm FDSOI. To enable agile dynamic voltage and frequency scaling with high energy efficiency, the designs feature an integrated switched-capacitor DC-DC converter. A custom-designed SRAM-based cache operates in a wide 0.45-1V supply range. Techniques that enable low-voltage SRAM operation include 8T cells, assist techniques and differential read.

Summary slide from Professor Bora Nikolic’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and UC Berkeley)

Pushing the Envelope in Mixed-Signal Design Using FD-SOI – Boris Murmann, Professor, Stanford University, USA

If you’ve ever attended a talk by Professor Murmann, you know that he’s a really compelling speaker. His research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces. In this course, he’ll look at how FD-SOI technology blends high integration density with outstanding analog device performance. In same-generation comparisons with bulk, he’ll review the specific advantages that FD-SOI brings to the design of mixed-signal blocks such as data converters and switched-capacitor blocks. Following the review of such general benchmarking data, he’ll show concrete design examples including an ultrasound interface circuit, a mixed-signal compute block, and a mixer-first RF front-end.

Summary slide from Professor Boris Murmann’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and Stanford U.)

Key Info About the FD-SOI Tutorial Day

  • Event: Designing with FD-SOI Technologies
  • Where: Samsung Semiconductor’s Auditorium “Palace”, San Jose, CA
  • When: April 14th, 2017, 8am to 3pm
  • Cost: $475
  • Organizer: SOI Industry Consortium
  • Pre-registration required – click here to sign up on the SOI Consortium website.



Chenming Hu: SOI Can Empower New Transistors to 10nm and beyond

FinFET and FD-SOI transistors look different but share a common principal that allows MOSFETs to be scalable to 10nm gate length.

The good, old MOSFET is nearing its limits. Scaling issues and dopant-induced variations are leading to high leakage (Ioff) and supply voltage (Vdd),  resulting in excessive  power consumption and design costs. While these challenges have been increasing over time, they’ve finally gotten painful enough that the industry is ready to embrace new transistor structures.

The essence of the problem is that the leakage current does not flow along the Si-oxide interface, but nanometers below the interface  when the gate lengths (Lg) becomes very small. That leakage path is physically far from the gate even if the oxide were infinitely thin. The gate cannot shut off the leakage as if the oxide were nanometers thick. Essentially the MOSFET becomes a resistor. Ioff and variations got worse and worse with Lg reductions.

The solution is new MOSFET structures, in which there is no Si far (more than nanometers) from the gate(s). In other words, the transistor body must be ultra thin. Body doping becomes optional.

Both FinFETs and FD-SOI devices are ultra-thin-body transistors. As such, compared to traditional planar bulk CMOS, they both provide:

  • Higher speed and lower leakage
  • Lower supply voltage (Vdd) and power consumption
  • Further scaling and lower cost
  • Better sub-threshold swing and scaling
  • No random dopant fluctuation (RDF), less variability
  • Better mobility, especially for future sub-threshold design


The FinFET body is a thin fin and the thin body is controlled from three sides instead of just the top.

FinFET is easy to scale because leakage is well suppressed if the fin thickness is equal to or less than Lg. Thin fins can be made with the same gate patterning/etching tools.

While our original FinFET work was on SOI wafers, a few years later (2003), Samsung presented a way to manufacture them on bulk substrates. There is an advantage to continued use of  bulk substrates; however, FinFET on bulk requires heavy implant below the fin to suppress leakage and that requires tradeoffs with FinFET performance.


When built on SOI, the FinFET does not suffer from leakage below the fin. Building FinFETs on SOI also confers certain advantages in simplifying manufacturing. The choice will be made by performance and comparisons.

Planar FD-SOI

Planar FD-SOI requires SOI wafers with a very, very thin top layer of silicon.  When we first invented the concept in 2000, the availability of such SOI substrates was the major obstacle. The final silicon layer thickness had to be about a quarter to a third of the gate length.

However, Soitec has surmounted the wafer challenge and with that, commercial production can now become a reality.

The FD-SOI approach can save the fabs and designers significant investment. Existing chip designs and associated IP can be ported with minimum effort, starting today at the 28nm node.

While FinFETs have a larger Ion, FD-SOI has a good back-gate bias option, which make it particularly interesting for low-power applications.


This is a very exciting time for the industry. Although it may seem that the industry is splitting into FinFETs and FD-SOI camps, both approaches use body thickness as the new scaling parameter, and can use undoped body for high performance chips without RDF. Both allow MOSFETs to be scaled beyond traditional MOSFET’s limit. And both can derive substantial benefits from SOI wafers. Real choice is good news because competition will bring the best out of both new transistor technologies.


Important News Comes Out of Recent FD-SOI Workshop

The SOI Consortium’s 6th FD-SOI workshop, held just after ISSCC, yielded some exciting news. Most of the presentations are freely available for downloading from the SOI Consortium website. Here are the highlights.


In a terrific presentation by Giorgio Cesana, Marketing Director at STMicroelectronics, he revealed that the company would be releasing a major product line based on planar FD-SOI at the 28nm node this year. Prototypes will be ready in June.

The objective, he said, is “…to have a compelling technology offer for the mobile application processor speed race.”

And compelling it is: their 28nm FD-SOI technology performances is 61% higher than comparable bulk technology at 1V. It gets even more interesting at lower Vdd – boasting a 550% improvement at 0.6V.


Slide 32 from ST's presentation

Slide 32 from ST’s presentation, 28 & 20nm FDSOI Technology Platforms, given at the SOI Consortium’s 6th FD-SOI Workshop (Feb. 24, 2012).


Check out the presentation – it’s got excellent descriptions, detailed roadmaps (look for products on 20nm FD-SOI in 2014), and clear comparisons. Topics include:

  • 28FDSOI positioning vs. bulk technologies
  • Design methodology and EDA flow
  • From spice models to product: migration methodology from Bulk to FDSOI
  • Biasing techniques on FDSOI
  • FDSOI ST design environment
  • 20FDSOI development track


In FD-SOI Design Portability, Betina Hold, Senior Principal for Silicon R&D at ARM in San Jose emphasized the ease of porting existing designs from bulk to FD-SOI.

FD-SOI, she concluded, is perfect for high-performance, low-power mobile apps.

Here are the main points she made:


Slide 29 from ARM's presentation

Slide 29 from ARM’s presentation, FDSOI Design Portability, given at the SOI Consortium’s 6th FD-SOI Workshop (Feb. 24, 2012).


(You can also read ARM’s perspective on the ease of porting from bulk to FD-SOI in a recent ASN article by the company’s Director of SOI Technology, Jean-Luc Pelloie.)


There were two presentations from IBM, addressing the two major flavors of fully-depleted architectures on SOI: planar FD-SOI, and FinFETs on SOI.

The presentation entitled Recent Advances in FDSOI given by Bruce Doris, Manager of Device Integration at IBM Research, reviewed various device structures. He presented new data indicating that FD-SOI performance is competitive for high performance and at a much shorter gate lengths (Lg), and will scale well beyond 20nm.

FINFET on SOI presented by Terence Hook, Senior Technical Staff Member at IBM, compared with both clarity and depth the characteristics and manufacturability of FinFETs on SOI and bulk with other SOI and bulk structures.


In a very in-depth presentation, FDSOI strain options FDSOI for 20nm and below, Olivier Faynot, who leads the Innovative Devices Lab at CEA-Leti, demonstrated how most of the existing techniques used on bulk technology are compatible with FDSOI. However, he emphasized that FDSOI devices already meet high performance requirements, especially at the circuit level. A unique feature of FDSOI for future nodes, he noted, is that strained SOI wafers (sSOI – wherein the top layer of silicon is strained at the wafer level) are particularly effective in giving NMOS a boost  (Ion NFET 1.4mA/µm – PFET 1.2 mA/µm @ Ioff 100nA/µm).


Enabling Substrate Technology for a Large Volume FD Standard, presented by Christine Pelissier, Director of Business Operations at SOI wafer manufacturer Soitec, gave a broad view of the both the technological and volume supply requirements for the wafers. Soitec is now manufacturing wafers for FDSOI in which the top silicon is controlled to within +/-5 angstroms.

She looked both at the wafers used in FDSOI as well as the partially depleted (PD) SOI wafers which have been in high-volume production for over a decade. She then went on to explain the key features in wafers for planar FDSOI (which Soitec refers to as FD2D) and in wafers for SOI-based FinFETs (FD3D).


Slide 8 from Soitec's presentation

Slide 8 from Soitec’s presentation, Enabling Substrate Technology for a Large Volume Fully Depleted Standard, given at the SOI Consortium’s 6th FD-SOI Workshop (Feb. 24, 2012).


Other highlights

Two presentations are not available online. Brian Chen of Agilent (Accelicon) presented 20nm ETUTBB-FDSOI Rev3 Models. (Note that 20nm FD-SOI logic evaluation model cards are now available through SOI Consortium in cooperation with Accelicon/Agilent. An NDA is required.)

Professor Borivoje Nikolic from UC Berkeley presented Microprocessor Design in FD-SOI.  This showed their design of a Planar FDSOI microprocessor that will be taped out later this year.

In all, this 6th workshop acknowledged the reality of Planar FDSOI technology starting with the 28nm node. There were plenty of relevant questions and discussions, confirming the promise FDSOI holds as a cost-effective and reliable solution.

As Horacio Mendez, Executive Director of the SOI Consortium concluded, this workshop was great. “We’ve been offering these workshops for over two years,” he said. “The community has taken Fully Depleted SOI from a technical advantage in the lab to a technical advantage on mobile products (as presented by ST). The cost, power, performance and manufacturability of FD SOI is a significant driving force.”


SOI Luminaries Shine in IEDM Awards

Of those receiving top awards at the IEDM last month, over half (!) are stars of the SOI community. Wow.

I discovered this while putting together the new listing of SOI-based papers at IEDM (don’t miss the summaries & links now posted in ASN’s most recent PaperLinks).

At the IEDM, the IEEE also awarded the title of “Fellow” to more major figures in the SOI world – see that article in ASN#15.

The IEDM is considered by many to be the most prestigious of the industry’s conferences. Here’s the “SOI list” of the most recent award winners.

2010 IEEE Cledo Brunetti Award

To: Ghavam G. Shahidi, IBM T.J. Watson Research Center

“For contributions to and leadership in the development of silicon-on-insulator CMOS technology.”

Ghavam Shahidi has been the driving force in making SOI a manufacturable reality and an integral component of today’s microelectronics.  He is currently the director of Silicon Technology at the IBM T.J. Watson Research Center.

2010 IEEE Andrew S. Grove Award

To: Bijan Davari, IBM T.J Watson Research Center

“For contributions to high performance deep-submicron CMOS technology.”

To create faster, higher-function and low-power microprocessor chips, Bijan Davari and his research team at IBM spearheaded critical changes in chip design to take advantage of new semiconductor materials and processes, including SOI.  He is currently vice president of Next Generation Computing Systems/Technology at the IBM T.J. Watson Research Center.

2010 IEEE Frederik Philips Award

To: John E. Kelly III, IBM

“For leadership in the development and commercialization of silicon technology and for forging industry-university partnerships for semiconductor research and development.”

John E. Kelly III is an executive whose strategic vision has led IBM to major technology breakthroughs and partnerships that have set the pace for the semiconductor industry, including bringing SOI to the high-performance microprocessor market. He is currently senior vice president and director of research at IBM Research.

2010 IEEE Kiyo Tomiyasu Award

To: Tsu-Jae King Liu, University of California at Berkeley

“For contributions to nanoscale MOS transistors, memory devices, and MEMs devices.”

Tsu-Jae King Liu is a researcher who co-invented the FinFET, and who has contributed to improving microelectromechanical systems (MEMS) technology and CMOS. She is currently the Conexant Systems Distinguished Professor at the University of California, Berkeley, where she is also the College of Engineering’s Associate Dean for Research. (Click here to see the FDSOI articles she’s contributed to ASN.)

2009 Roger A. Haken Best Student Paper Award

To: Perrine Batude of CEA-LETI-MINATEC for Advances in 3D CMOS Sequential Integration

The winning paper (awarded at IEDM 2010) is based on Perrine Batude’s PhD dissertation, which she completed at Léti in late 2009.  Leveraging FD-SOI, the work in this paper demonstrates the possibility of obtaining regular 2D performance within a 3D sequential integration scheme. It further investigates the unique features of low temperature processes. Finally, it quantifies for the first time, the electrostatic coupling between the layers. Dr. Batude has a degree from the Ecole Nationale Supérieure de Physique de Grenoble, and specializes in the 3D integration of elementary functions. Léti hired her as soon as she finished her dissertation.

2010 EDS J.J. Ebers Award

To: Mark E. Law, University of Florida

“For contributions to widely used silicon integrated circuit process modeling”

Dr. Law is Professor and College of Engineering Associate Dean of Academic Affairs for the Department of Electrical and Computer Engineering at the University of Florida. Some of his earlier work related to materials and doping was helpful to the advancement of SOI.

A pretty impressive line-up, don’t you think?  Leaders in the research community are certainly impressed with the work of SOI luminaries. But were you surprised by how many were recognized?  Leave a comment and share your thoughts.

(Photos courtesy IBM, UC Berkeley, Leti, UFlorida)


The right choice for 22nm SRAM

What is the best transistor structure to meet SRAM performance and yield requirements at the 22nm node? The semiconductor device research group at UC Berkeley pioneered the FinFET structure in 1998. Now SOI-based FinFETs lead the field of candidate structures to eventually replace the planar bulk MOSFET. In the near term, yield and manufacturability may trump performance for high-volume markets, however.

Our work recently presented at the 2009 IEEE SOI Conference indicates that a planar fully depleted (FD) structure on very thin-BOX (~10nm thick) is a compelling candidate. Specifically, we found that for 6T-SRAM cells at the 22nm node:

  • planar FD-SOI structures on thin-BOX are significantly better than planar bulk-Si structures, in terms of both performance and yield;
  • although planar FD-SOI structures on thin-BOX cannot yet match FinFETs in performance, their performance is adequate and they are easier to manufacture for high-volume applications demanding high yields.

Read More


Through the Back Gate

Might the Back-Gated FD-SOI MOSFET be the ultimate transistor structure?

The fully depleted silicon-on-insulator (FD-SOI) MOSFET structure has been proposed for scaling CMOS technology to sub-45nm nodes. This is because short-channel effects (manifested in increasing off-state leakage with increasing drain bias and with decreasing gate length) are well suppressed in a FD-SOI MOSFET when the body thickness (TSi) is less than or equal to one-fourth of the gate length (LG). Read More