Silicon Europe (an alliance of Europe’s leading micro- and nanoelectronics clusters) and the SOI Consortium have organized an SOI Workshop on the 7th of July 2015, during the 10th Silicon Saxony Day in Dresden.
Here’s the agenda:
The workshop, which runs from 1:30 – 4:30, will be held in English. There is an entry fee (waived for students) for Silicon Saxony Day, but once you’re in, the SOI Workshop is free.
For the first time ever, Semicon Europa will be held in Grenoble this year, and FD-SOI will be a major part of it (website link here). With more than 5000 visitors and 350 exhibitors, Semicon Europa is the greatest annual event for the European microelectronics industry.
And Grenoble can fairly be considered the epicenter of all things SOI: it really took off when Leti researcher Michel Bruel invented the Smart CutTM technology there for manufacturing SOI wafers in the early 1990’s. That was then spun off to Soitec up the road, and the rest is history in the making. In fact, Forbes recently recognized Grenoble as one of the Top 5 Most Inventive Cities in the world.
So from now on, Semicon Europa will alternate between Dresden, Germany (home to GlobalFoundries’ fabs) and Grenoble, France.
Happily this is coinciding with an industry upturn, so Semi’s signed up 25% more exhibitors than last year. In addition to the exhibition floor, the 3-day event will also host over 300 speakers at over 70 conferences and more than 100 hours of technology sessions and presentations. This is no longer your quiet Euro-equipment show – this is a dynamic happening covering the entire supply chain, with a big emphasis on innovation and applications.
For those attending the popular Fab Managers Forum, the opening keynote will be made by Soitec founder and CEO André-Jacques Auberton-Hervé. In addition to heading up the world’s largest SOI wafer manufacturer, Dr. Auberton-Hervé is a member of the EC’s High-Level Group on Key Enabling Technologies (KET) and of the Electronic Leaders Group (ELG), which is in charge of implementing the European Union’s “10/100/20” strategy (they’re looking to leverage €10 Billion Public/Private Funding for a €100 Billion investment from industry for manufacturing to capture 20% of the semiconductor market value for Europe by 2020). As we reported here in ASN earlier this year, SOI-based apps are an important part of all this.
In the abstract for his Semicon presentation, Dr. Auberton-Hervé indicates he’ll describe the ELG implementation plan focused on demand accelerators (IoT, mobile convergence), supply chain strengthening, and an enhanced framework development across Europe. The Pilot Lines initiative was started in 2012, and industry is ready to invest now, he notes, with 5 pilot lines in progress, and numerous projects submitted. He’ll highlight how manufacturing performance is key in the European semiconductor industry, from materials and equipment to components design and wafer production.
FD-SOI at the Semicon Europa Low Power Conference
The key Semicon Europa event for the FD-SOI ecosystem will be The Low Power Conference, which features a cast of heavy hitters (abstracts for the talks and speaker bios are available here.) It kicks off on Tuesday afternoon (7 September) with a market analysis by ST COO Jean-Marc Chery, exploring solutions for mobile to servers and IoT.
Next up, Manfred Horstmann, GlobalFoundries’ Director of Products and Integration in Dresden will focus on SOCs for at 28/20nm. He’s using the term “ET-SOI” with BB (back bias) options. The ET stands for Extremely Thin SOI – it’s the term IBM first used for FD-SOI, but the two terms are now used seemingly interchangeably. As Horstmann notes in the conference abstract, “Being a planar device, ET-SOI devices allow the continuation of previous nodes manufacturing and design experience. Vt-tunability and low GIDL currents are a clear advantage of ET-SOI BB devices for SoC applications, too.” He’ll conclude with an outlook on FinFETs.
Thomas Skotnicki Fellow and Director of Advanced Devices at STMicroelectronics and all around giant of FD-SOI (and in particular ST’s flavor: ultra-thin box and body aka UTBB) has what sounds like a groundbreaking IoT talk. Beyond FD-SOI, he’ll cover how the technology will be used in conjunction with energy harvesting, storage, power management, sensors and MEMS. He’s got a low-power mobile app example to show us, too.
David Jacquet of ST will address design, showing among other things how FD-SOI opens the way to new opportunities like Wide DVFS and dynamic leakage management. He’ll be detailing the key IP for implementing those technologies. (He’s got a great video on FD-SOI design techniques, btw – click here for more on that.)
Soitec CTO Carlos Mazure will cover the range of substrate solutions for devices across the mobile space, including RF, FD-SOI and SOI FinFET.
Wednesday morning, the conference continues with more from ST, and a must-see talk on FD-SOI and IoT costs and projections by Handel Jones of IBS. (If you’ve missed his excellent pieces here in ASN, you’ll find them all here.)
The rest of the afternoon will focus on design tools and applications, with talks from Cadence, ANSYS, Docea, HP (two talks from them), Ericsson, Schneider and Sorin (medical devices).
ASN will be there – follow us on Twitter for live coverage – and we’ll bring you more details of the key talks in the weeks to come.
Power and 3DI
A couple of other last notes if you’re planning a trip to Semicon Europa. On Wednesday afternoon (8 September), a 3D Integration Session (details here) will cover recent updates on 3D circuit and process technologies. Following an introduction by Ionut Radu, Soitec Senior Scientist, speakers from TSMC, imec, Leti, EV Group, Entegris, Fujifilm and Rockwood will address the status of 3D circuits, including 3D TSV and monolithic 3D integration schemes, manufacturing challenges and readiness for application specific systems.
Another terrific Semicon Europa event for the advanced substrates community will be the Power Electronics Conference: the ultimate path to CO2 reduction. Topics cover GaN, GaN-on-Si, SiC and SOI. Renault, Leti, Schneider Electric, ST, Infineon, Yole, Fairchild, and Siltronic will be presenting, as well as Arnaud Rigny of Soitec, who’ll will give a talk on smart substrates for smart power. This all takes place on Wednesday and Thursday, the 8th and 9th of September. Details can be found here.
Hope to see you in Grenoble!
As we noted in the previous post (click here if you missed it), 2014 should be a terrific year for the greater SOI community.
But before we look forward (which we’ll do in an upcoming post), let’s continue considering where we’ve been and some of the highlights of the last year. In fact, there was so much happening in 2013 that it’s taken two posts – the previous was about FD-SOI; in this post we’ll review RF-SOI and SOI-FinFETs.
The RF-SOI Juggernaut
SOI for front-end RF solutions rapidly gained ground throughout the industry in 2013, with announcements by Peregrine, Magnachip, ST, IBM, TowerJazz, Skyworks, Grace Semi and RDA in China, and more. In fact, industry research firm Yole Développement found that more than 65 percent of substrates used in fabricating switches for handsets are SOI based. And the SOI wafer leader Soitec has said that chips built on its SOI wafers were found in over half of the smartphones and tablets in the market worldwide. This shows the massive adoption of RF-SOI for this part of the market, which is experiencing double-digit growth.
In April, SemiconductorEngineering reported that part of Qualcomm’s RF360 front-end solution is on SOI, a “shot across the bow”, according to StrategyAnalytics.
In June, ST announced a new manufacturing process, known as H9SOI_FEM, for production of complete integrated front-end modules.
In October, Toshiba chimed in with a new RF-SOI product announcement, noting that it had been using SOI for RF since 2009.
In December, SOI wafer leader Soitec announced that they’re in high-volume manufacturing of a new flavor of SOI wafers for advanced RF apps like LTE/4G. In fact, these new wafers are already used in manufacturing by most of the leading RF foundries in front-end modules for 4G and LTE mobile computing and communication applications. Developed with UCL, they’re called Enhanced Signal Integrity™ (eSI) substrates, and enable cost-effective and high-performance RF devices. They are the first ‘trap-rich’ type of material in full production.
14nm SOI-FinFETs Get Real
In November, IBM posted a piece in ASN entitled FinFET on SOI: Potential BecomesReality. The IBM team shared impressive hardware data for 14nm SOI-FinFETs. SOI eliminates the need for doping, they remind us, which enables FinFETs to attain unsurpassed threshold voltage (Vt) matching between transistor pairs. (Vt is the point at which a transistor switches on or off.)
They found, on top of the well-documented improvements in Vt matching for logic and SRAM devices, an even more dramatic matching improvement for thick-dielectric devices. These are used for analog and IO devices, and also in DRAM — where this opens the door to various optimizations and enables fundamental area scaling.
For the classic 6T SRAM, improved Vt matching means you can lower the minimum operating voltage. For their SRAM array, the IBM team showed minimum operating voltage down to 400mV, with full read and write capability. That’s as good or better than any yet reported, and it was done without using chip-specific tuning techniques. The bottom line: real SOI-FinFET SRAMs can operate at very low voltages.
Representative bulk-based (junction-isolated) and SOI-based (dielectric-isolated) fin profiles, and corresponding empirical degradation in electrostatics. The tapered shape of the bulk fin shown results in nonuniform current flow and poorer low-voltage operation and self-gain than the more ideally shaped SOI FinFET. (Courtesy: IBM)
Manufacturing a FinFET on SOI also enables a more ideal fin profile. In turn, this near-ideal shape delivers performance well in line with the “theoretical” benefits of FinFET technology. It avoids the need for the more tapered shape seen on bulk FinFETs that trade-off some electrical performance for manufacturability.
IBM’s results exhibit excellent correspondence between the actual hardware and the expectations, which include far less dependence on the supply voltage than conventional planar technology.
The various pieces contributed to ASN by IBM about SOI-FinFETs are amongst our all-time most popular posts. We’ve also shared some of them with the folks over at SemiMD, where they continue to generate enormous interest.
So we’ll look forward to hearing more about SOI-FinFETs in 2014, too!
Another RF-SOI solution is making headlines. Leveraging SOI, Toshiba has announced an SP10T RF antenna switch for the smartphone market. The company says it achieves the industry’s lowest insertion loss and smallest size.
The company credits its new generation TaRF5 process, the latest in its line of Toshiba-original TarfSOI™ (Toshiba advanced RF SOI) processes. The new TaRF5 process delivers approximately 25% lower insertion loss (at 2.7 GHz) and approximately 40% size reduction (for SP10T), compared to the comparable devices fabricated with the TaRF3 process.
Sample shipments of the SP10T (which stands for Single Pole Ten Throw Switch) have now started.
The TarfSOI™ process was first developed in 2009. The SOI advantage, says Toshiba, is the insulating film under the channel of the MOSFET, reducing stray capacity to improve speed and power saving of the CMOS LSI. The latest improvements can lead to longer battery operating time and smaller mounting space, which can also contribute to smaller sizes for products in which they are used, says the company.
Since the first TarfSOI generation, Toshiba has been continually developing new generation processes and devices offering improved performance. The company explains that RF antenna switch requirements for the current LTE and next-gen LTE-Advanced are leaning towards multi-port and complex functions. That’s why, to meet those market demands, Toshiba plans to continue to develop products with low insertion loss and smaller sizes.
SOI for front-end RF solutions is rapidly gaining ground throughout the industry. In recent months, announcements have been made by Peregine, Magnachip, ST, IBM, TowerJazz, Skyworks, Grace Semi and RDA in China, and more. In fact, industry research firm Yole Développement recently found that more than 65 percent of substrates used in fabricating switches for handsets are SOI based. And the SOI wafer leader Soitec has said that chips built on its SOI wafers were found in over half of the smartphones and tablets in the market worldwide. This shows the massive adoption of RF-SOI for this part of the market, which is experiencing double-digit growth. Who’s next?
In the latest ASN posting by Dr. Eric Mounier of Yole Developpement, “SOI for MEMS: A Promising Material”, he notes that SOI MEMS is growing at a CAGR (2011-2015) of 15.6%, compared to 8.1% for bulk silicon-based solutions.
MEMS designers are doing amazing things on SOI – which would explain that impressive growth rate.
One of my favorites is Debiotech’s tiny insulin NanopumpTM targeting diabetes, fabbed by ST. As Debiotech’s Laurent-Dominique Piveteau noted, “…the use of SOI wafers for fabricating the Nanopump MEMS device has significant medical and economic advantages. The SOI-based structure allows for the highest reliability in the smallest possible package, enabling very tight control and precision of the pumping mechanism. The flow rate is steady, and it is insensitive to pressure, temperature, viscosity and aging. It also offers extreme dosing precision.”
Reasons cited by other contributors for using SOI for MEMS include:
But the bottom line is that it’s the most cost-effective solution for their state-of-the-art MEMS devices.
MEMS also figure in two of the most recent ASN Buzz postings:
In the next few weeks, we’ll also be posting a new article by Soitec on their Smart Stacking(tm) technology for the next generation of MEMS with pre-etched cavities, among other things.
If you’d like to see more of the why’s and wherefore’s of SOI-MEMS apps, just type “MEMS” into ASN’s search engine. You’ll get dozens of pieces from and about leaders like ST, ADI, Denso, VTI, Tronics, IBM and more.
It’s a pretty fragmented world, still, so if you know cool SOI-MEMS apps we should be covering, would you let me know?
A new Yole report highlights growth of SOI MEM S.
Although MEMS technologies are not driven by CD shrinking as ICs, that does not mean MEMS do not undergo strong technological evolutions. The ever-growing MEMS markets, today mostly driven by consumer applications, now have to be performance-driven, cost-driven and size driven.
SOI wafers are a promising substrate for MEMS manufacturing. We estimate the SOI market for MEMS devices will be close to $100M by 2015 (see Figure 1). That represents a CAGR (2011-2015) of 15.6% for SOI, compared to 8.1% for bulk silicon-based solutions.
One main reason for using SOI is to have more design freedom. Tronics, for example is using SOI with High Aspect Ratio Micromachining technology. This technology was developed to manufacture high performance custom inertial sensors (accelerometers and gyroscopes).
Other reasons cited for choosing an SOI-based solution for MEMS include the need for the smallest possible package, very tight control and precision of the structure, ability to withstand high pressure and temperature, long product lifetime, smallest possible die size and reduced cost.
Additional features in SOI wafers can further simplify MEMS design and manufacturing. For example, “cavity-SOI”, in which the SOI wafer has pre-etched cavities, enables the MEMS manufacturers to focus on their core competencies in reducing development time, which in turn can even lower production costs. Some MEMS manufacturers have found that pre-etched SOI cavities combined with dry etching simplifies the release of the devices.
MEMS manufacturers using cavity-SOI include VTI Technologies, Invensense and other players in the seismic accelerometer (Tronics) and pressure sensor markets.
Figure 2 shows a roadmap for SOI wafers for MEMS. From “traditional” SOI, we are now using SOI with pre-etched cavities. Further developments will allow the realization of SOI wafers with trench isolation, cavities and Through Silicon Vias (TSV).
Suppliers of other substrate solutions are following similar added-value paths. Glass, for example, can be used as a thin wafer carrier for wafer level capping and/or packaging with Through Glass Vias interconnect.
Overall, we believe substrates will provide additional functionalities in the future, enabling more integrated MEMS devices.
Yole looks for a wide range of MEMS-based products to be introduced this year.
Despite the current economic situation, a piece of good news is that innovation will not come to a halt in 2009: we expect that this will be one of the greatest years ever for new product introductions.
The MEMS market in general is still very fragmented in terms of companies and products. Read More